Message ID | 1422029835-4696-5-git-send-email-greg.bellows@linaro.org |
---|---|
State | Superseded |
Headers | show |
On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote: > Added CP register definitions for SP_EL1 and SP_EL2. > > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > --- > > v1 -> v2 > - Remove unnecessary accessfn for SP_EL1/2 > - Revert SP_EL0 accessfn name to sp_el0_access > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 29f3b62..79c54a9 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .access = PL1_RW, .accessfn = sp_el0_access, > .type = ARM_CP_NO_MIGRATE, > .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, > + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, > + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, > { .name = "SPSel", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > .type = ARM_CP_NO_MIGRATE, > @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .access = PL2_RW, .writefn = vbar_write, > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), > .resetvalue = 0 }, > + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, > + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, > + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, > REGINFO_SENTINEL > }; As I was assembling my target-arm queue I found that this patch and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict; since this patch happened to be earlier in the queue than that one, I've resolved this by adding changes to the 'split' patch which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in line with how we handled the SP_EL0 regdef. thanks -- PMM
On Tue, Jan 27, 2015 at 1:03 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote: > > Added CP register definitions for SP_EL1 and SP_EL2. > > > > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > > > --- > > > > v1 -> v2 > > - Remove unnecessary accessfn for SP_EL1/2 > > - Revert SP_EL0 accessfn name to sp_el0_access > > --- > > target-arm/helper.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index 29f3b62..79c54a9 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > > .access = PL1_RW, .accessfn = sp_el0_access, > > .type = ARM_CP_NO_MIGRATE, > > .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, > > + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, > > + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, > > + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, > > { .name = "SPSel", .state = ARM_CP_STATE_AA64, > > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > > .type = ARM_CP_NO_MIGRATE, > > @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > > .access = PL2_RW, .writefn = vbar_write, > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), > > .resetvalue = 0 }, > > + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, > > + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, > > + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, > > REGINFO_SENTINEL > > }; > > As I was assembling my target-arm queue I found that this patch > and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict; > since this patch happened to be earlier in the queue than that > one, I've resolved this by adding changes to the 'split' patch > which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in > line with how we handled the SP_EL0 regdef. > > thanks > -- PMM > That makes sense.
diff --git a/target-arm/helper.c b/target-arm/helper.c index 29f3b62..79c54a9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .accessfn = sp_el0_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL };