| Message ID | 1477538129-118465-16-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | New |
| Headers | show |
Some kind of commit message body, please. On Thu, Oct 27, 2016 at 11:15:20AM +0800, Heyi Guo wrote: > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Heyi Guo <guoheyi@huawei.com> > --- > .../Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c > index 07dae5f..61473e8 100644 > --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c > +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c > @@ -226,7 +226,7 @@ GetCacheSocketStr ( > OUT CHAR16 *CacheSocketStr > ) > { > - UINTN CacheSocketStrLen = 0; > + UINTN CacheSocketStrLen; This does not look functionally related to the described changeset. Should is be a separate bugfix? > > if(CacheLevel == CPU_CACHE_L1_Instruction) > { > @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( > CACHE_SRAM_TYPE_DATA CacheSramType = {0}; > > CoreCount = 16; // Default value is 16 Core > - CacheSize = 0; This too looks unrelated. > > // > // Set Cache Configuration > @@ -490,6 +489,7 @@ AddSmbiosProcessorTypeTable ( > CHAR16 *CpuVersion; > STRING_REF TokenToUpdate; > > + UINT64 *ProcessorId; > Type4Record = NULL; > ProcessorManuStr = NULL; > ProcessorVersionStr = NULL; > @@ -614,6 +614,8 @@ AddSmbiosProcessorTypeTable ( > Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; > > Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); > + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); > + *ProcessorId = ArmReadMidr(); > > OptionalStrStart = (CHAR8 *) (Type4Record + 1); > UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart); > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..61473e8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -226,7 +226,7 @@ GetCacheSocketStr ( OUT CHAR16 *CacheSocketStr ) { - UINTN CacheSocketStrLen = 0; + UINTN CacheSocketStrLen; if(CacheLevel == CPU_CACHE_L1_Instruction) { @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( CACHE_SRAM_TYPE_DATA CacheSramType = {0}; CoreCount = 16; // Default value is 16 Core - CacheSize = 0; // // Set Cache Configuration @@ -490,6 +489,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate; + UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL; @@ -614,6 +614,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); + *ProcessorId = ArmReadMidr(); OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <guoheyi@huawei.com> --- .../Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)