@@ -7435,8 +7435,11 @@ encode_arm_shift (int i)
int index;
for (index = 0; index <= i; ++index)
{
- gas_assert (inst.operands[index].present);
- if (inst.operands[index].isreg && inst.operands[index].reg == REG_PC)
+ /* Check the operand only when it's presented. In pre-UAL syntax,
+ if the destination register is the same as the first operand, two
+ register form of the instruction can be used. */
+ if (inst.operands[index].present && inst.operands[index].isreg
+ && inst.operands[index].reg == REG_PC)
as_warn (UNPRED_REG ("r15"));
}
new file mode 100644
@@ -0,0 +1,11 @@
+# name: Two register form of data processing instruction with register shifted register operand
+# as:
+# objdump: -dr
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: e0855014 add r5, r5, r4, lsl r0
+ 4: e0855014 add r5, r5, r4, lsl r0
new file mode 100644
@@ -0,0 +1,5 @@
+ .arch armv7-a
+ .text
+ # PR 20827
+ add r5, r4, lsl r0
+ add r5, r5, r4, lsl r0