| Message ID | 1490015485-53685-8-git-send-email-chenhui.sun@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | D02/D03 platforms bug fix | expand |
On Mon, Mar 20, 2017 at 09:11:11PM +0800, Chenhui Sun wrote: > CPM should also be 1 when CCA is 1. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: wanglijun <wanglijun@huawei.com> > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> IMO these three paches changelog could be improved by showing the DSDT snippet that conflicts and the test output. So that people coming later why have a similar issue find the solution. Graeme > --- > Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > index bcd31d6..8f38359 100644 > --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > @@ -205,8 +205,8 @@ > Read Allocate : 0 > Override : 0 > [0002] Reserved : 0000 > -[0001] Memory Flags (decoded below) : 00 > - Coherency : 0 > +[0001] Memory Flags (decoded below) : 01 > + Coherency : 1 > Device Attribute : 0 > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000001 > @@ -234,8 +234,8 @@ > Read Allocate : 0 > Override : 0 > [0002] Reserved : 0000 > -[0001] Memory Flags (decoded below) : 00 > - Coherency : 0 > +[0001] Memory Flags (decoded below) : 01 > + Coherency : 1 > Device Attribute : 0 > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000002 > -- > 1.9.1 >
Subject should include something indicating that it resolves the problem, rather than introducing it :) In this case, just "... fix IORT test ..." would be fine. I could fold that in myself on commit, but since Graeme asked for more detailed commit message as well, can you do that at the same time please? Regards, Leif On Mon, Mar 20, 2017 at 09:11:11PM +0800, Chenhui Sun wrote: > CPM should also be 1 when CCA is 1. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: wanglijun <wanglijun@huawei.com> > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> > --- > Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > index bcd31d6..8f38359 100644 > --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > @@ -205,8 +205,8 @@ > Read Allocate : 0 > Override : 0 > [0002] Reserved : 0000 > -[0001] Memory Flags (decoded below) : 00 > - Coherency : 0 > +[0001] Memory Flags (decoded below) : 01 > + Coherency : 1 > Device Attribute : 0 > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000001 > @@ -234,8 +234,8 @@ > Read Allocate : 0 > Override : 0 > [0002] Reserved : 0000 > -[0001] Memory Flags (decoded below) : 00 > - Coherency : 0 > +[0001] Memory Flags (decoded below) : 01 > + Coherency : 1 > Device Attribute : 0 > [0004] ATS Attribute : 00000000 > [0004] PCI Segment Number : 00000002 > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -234,8 +234,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002