| Message ID | 20170831130830.12833-3-ard.biesheuvel@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Platform/OverdriveBoard: move device tree compilation into build | expand |
Adding Grant, On Thu, Aug 31, 2017 at 02:08:28PM +0100, Ard Biesheuvel wrote: > Clean up the device tree source file, by switching to Tianocore > conventions for line endings and whitespace etc, and by replacing > open coded values with symbol constants and/or phandle references. 1: All for the getting rid of open coding. 2: As for the line endings/whitespace, I am less convinced. It is its own (and very specific) file format, it is not edk2-specific, and just like (GNU)Makefiles and shellscripts they originated in a CR-free environment. / Leif > The resulting .dtb will likely not be identical at the bit level, but > the modifications are cosmetic only. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 957 ++++++++++---------- > 1 file changed, 467 insertions(+), 490 deletions(-) > > diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts > index 4039f666004a..81477fe43cdd 100644 > --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts > +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts > @@ -2,6 +2,7 @@ > * DTS file for AMD Seattle (Rev.B) Overdrive Development Board > * > * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. > + * Copyright 2015 - 2017 Linaro, Ltd. All Rights Reserved. > * > * This program and the accompanying materials are licensed and made available > * under the terms and conditions of the BSD License which accompanies this > @@ -14,497 +15,473 @@ > * > */ > > +#define GIC_SPI 0 > +#define GIC_PPI 1 > + > +#define IRQ_TYPE_NONE 0 > +#define IRQ_TYPE_EDGE_RISING 1 > +#define IRQ_TYPE_EDGE_FALLING 2 > +#define IRQ_TYPE_LEVEL_HIGH 4 > +#define IRQ_TYPE_LEVEL_LOW 8 > + > +#define GIC_CPU_MASK(num) (((1 << (num)) - 1) << 8) > + > /dts-v1/; > > / { > - model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; > - compatible = "amd,seattle-overdrive", "amd,seattle"; > - interrupt-parent = <0x1>; > - #address-cells = <0x2>; > - #size-cells = <0x2>; > - > - interrupt-controller@e1101000 { > - compatible = "arm,gic-400", "arm,cortex-a15-gic"; > - interrupt-controller; > - #interrupt-cells = <0x3>; > - #address-cells = <0x2>; > - #size-cells = <0x2>; > - reg = <0x0 0xe1110000 0x0 0x1000>, > - <0x0 0xe112f000 0x0 0x2000>, > - <0x0 0xe1140000 0x0 0x2000>, > - <0x0 0xe1160000 0x0 0x2000>; > - interrupts = <0x1 0x9 0xf04>; > - ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; > - linux,phandle = <0x1>; > - phandle = <0x1>; > - > - v2m@e0080000 { > - compatible = "arm,gic-v2m-frame"; > - msi-controller; > - reg = <0x0 0x80000 0x0 0x1000>; > - linux,phandle = <0x4>; > - phandle = <0x4>; > - }; > - }; > - > - timer { > - compatible = "arm,armv8-timer"; > - interrupts = <0x1 0xd 0xff04>, > - <0x1 0xe 0xff04>, > - <0x1 0xb 0xff04>, > - <0x1 0xa 0xff04>; > - }; > - > - smb { > - compatible = "simple-bus"; > - #address-cells = <0x2>; > - #size-cells = <0x2>; > - ranges; > - /* > - * dma-ranges is 40-bit address space containing: > - * - GICv2m MSI register is at 0xe0080000 > - * - DRAM range [0x8000000000 to 0xffffffffff] > - */ > - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; > - > - clk100mhz_0 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <100000000>; > - clock-output-names = "adl3clk_100mhz"; > - }; > - > - clk375mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <375000000>; > - clock-output-names = "ccpclk_375mhz"; > - }; > - > - clk333mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <333000000>; > - clock-output-names = "sataclk_333mhz"; > - linux,phandle = <0x2>; > - phandle = <0x2>; > - }; > - > - clk500mhz_0 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <500000000>; > - clock-output-names = "pcieclk_500mhz"; > - }; > - > - clk500mhz_1 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <500000000>; > - clock-output-names = "dmaclk_500mhz"; > - }; > - > - clk250mhz_4 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <250000000>; > - clock-output-names = "miscclk_250mhz"; > - linux,phandle = <0xd>; > - phandle = <0xd>; > - }; > - > - clk100mhz_1 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <100000000>; > - clock-output-names = "uartspiclk_100mhz"; > - linux,phandle = <0x3>; > - phandle = <0x3>; > - }; > - > - sata0_smmu: smmu@e0200000 { > - compatible = "arm,mmu-401"; > - reg = <0 0xe0200000 0 0x10000>; > - #global-interrupts = <1>; > - interrupts = /* Uses combined intr for both > - * global and context > - */ > - <0 332 4>, > - <0 332 4>; > - #iommu-cells = <2>; > - dma-coherent; > - }; > - > - sata1_smmu: smmu@e0c00000 { > - compatible = "arm,mmu-401"; > - reg = <0 0xe0c00000 0 0x10000>; > - #global-interrupts = <1>; > - interrupts = /* Uses combined intr for both > - * global and context > - */ > - <0 331 4>, > - <0 331 4>; > - #iommu-cells = <2>; > - dma-coherent; > - }; > - > - sata@e0300000 { > - compatible = "snps,dwc-ahci"; > - reg = <0x0 0xe0300000 0x0 0xf0000>; > - interrupts = <0x0 0x163 0x4>; > - clocks = <0x2>; > - dma-coherent; > - iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ > - }; > - > - sata@e0d00000 { > - status = "disabled"; > - compatible = "snps,dwc-ahci"; > - reg = <0x0 0xe0d00000 0x0 0xf0000>; > - interrupts = <0x0 0x162 0x4>; > - clocks = <0x2>; > - dma-coherent; > - iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ > - }; > - > - i2c@e1000000 { > - compatible = "snps,designware-i2c"; > - reg = <0x0 0xe1000000 0x0 0x1000>; > - interrupts = <0x0 0x165 0x4>; > - clocks = <0xd>; > - }; > - > - i2c@e0050000 { > - compatible = "snps,designware-i2c"; > - reg = <0x0 0xe0050000 0x0 0x1000>; > - interrupts = <0x0 0x154 0x4>; > - clocks = <0xd>; > - }; > - > - serial@e1010000 { > - compatible = "arm,pl011", "arm,primecell"; > - reg = <0x0 0xe1010000 0x0 0x1000>; > - interrupts = <0x0 0x148 0x4>; > - clocks = <0x3 0x3>; > - clock-names = "uartclk", "apb_pclk"; > - }; > - > - ssp@e1020000 { > - compatible = "arm,pl022", "arm,primecell"; > - reg = <0x0 0xe1020000 0x0 0x1000>; > - spi-controller; > - interrupts = <0x0 0x14a 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - }; > - > - ssp@e1030000 { > - compatible = "arm,pl022", "arm,primecell"; > - reg = <0x0 0xe1030000 0x0 0x1000>; > - spi-controller; > - interrupts = <0x0 0x149 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - num-cs = <0x1>; > - #address-cells = <0x1>; > - #size-cells = <0x0>; > - > - sdcard@0 { > - compatible = "mmc-spi-slot"; > - reg = <0x0>; > - spi-max-frequency = <20000000>; > - voltage-ranges = <3200 3400>; > - pl022,hierarchy = <0x0>; > - pl022,interface = <0x0>; > - pl022,com-mode = <0x0>; > - pl022,rx-level-trig = <0x0>; > - pl022,tx-level-trig = <0x0>; > - }; > - }; > - > - gpio@e1050000 { /* [0 : 7] */ > - compatible = "arm,pl061", "arm,primecell"; > - #gpio-cells = <0x2>; > - reg = <0x0 0xe1050000 0x0 0x1000>; > - gpio-controller; > - interrupt-controller; > - #interrupt-cells = <0x2>; > - interrupts = <0x0 0x166 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - }; > - > - gpio@e0020000 { /* [8 : 15] */ > - status = "disabled"; > - compatible = "arm,pl061", "arm,primecell"; > - #gpio-cells = <0x2>; > - reg = <0x0 0xe0020000 0x0 0x1000>; > - gpio-controller; > - interrupt-controller; > - #interrupt-cells = <0x2>; > - interrupts = <0x0 0x16e 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - }; > - > - gpio@e0030000 { /* [16 : 23] */ > - status = "disabled"; > - compatible = "arm,pl061", "arm,primecell"; > - #gpio-cells = <0x2>; > - reg = <0x0 0xe0030000 0x0 0x1000>; > - gpio-controller; > - interrupt-controller; > - #interrupt-cells = <0x2>; > - interrupts = <0x0 0x16d 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - }; > - > - gpio@e0080000 { /* [24] */ > - compatible = "arm,pl061", "arm,primecell"; > - #gpio-cells = <0x2>; > - reg = <0x0 0xe0080000 0x0 0x1000>; > - gpio-controller; > - interrupt-controller; > - #interrupt-cells = <0x2>; > - interrupts = <0x0 0x169 0x4>; > - clocks = <0x3>; > - clock-names = "apb_pclk"; > - }; > - > - ccp: ccp@e0100000 { > - compatible = "amd,ccp-seattle-v1a"; > - reg = <0x0 0xe0100000 0x0 0x10000>; > - interrupts = <0x0 0x3 0x4>; > - dma-coherent; > - amd,zlib-support = <0x1>; > - }; > - > - pcie: pcie@f0000000 { > - compatible = "pci-host-ecam-generic"; > - #address-cells = <0x3>; > - #size-cells = <0x2>; > - #interrupt-cells = <0x1>; > - iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; > - device_type = "pci"; > - bus-range = <0x0 0x7f>; > - msi-parent = <0x4>; > - reg = <0x0 0xf0000000 0x0 0x10000000>; > - interrupt-map-mask = <0xff00 0x0 0x0 0x7>; > - interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, > - <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, > - <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, > - <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, > - > - <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, > - <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, > - <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, > - <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, > - > - <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, > - <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, > - <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, > - <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; > - dma-coherent; > - dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; > - ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ > - <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ > - <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ > - }; > - > - pcie_smmu: smmu@e0a00000 { > - compatible = "arm,mmu-401"; > - reg = <0 0xe0a00000 0 0x10000>; > - #global-interrupts = <1>; > - interrupts = /* Uses combined intr for both > - * global and context > - */ > - <0 333 4>, > - <0 333 4>; > - #iommu-cells = <1>; > - dma-coherent; > - }; > - > - ccn@0xe8000000 { > - compatible = "arm,ccn-504"; > - reg = <0x0 0xe8000000 0x0 0x1000000>; > - interrupts = <0x0 0x17c 0x4>; > - }; > - > - gwdt@e0bb0000 { > - status = "disabled"; > - compatible = "arm,sbsa-gwdt"; > - reg = <0x0 0xe0bb0000 0x0 0x10000 > - 0x0 0xe0bc0000 0x0 0x10000>; > - reg-names = "refresh", "control"; > - interrupts = <0x0 0x151 0x4>; > - interrupt-names = "ws0"; > - }; > - > - kcs@e0010000 { > - status = "disabled"; > - compatible = "ipmi-kcs"; > - device_type = "ipmi"; > - reg = <0x0 0xe0010000 0 0x8>; > - interrupts = <0 389 4>; > - interrupt-names = "ipmi_kcs"; > - reg-size = <1>; > - reg-spacing = <4>; > - }; > - > - clk250mhz_0 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <250000000>; > - clock-output-names = "xgmacclk0_dma_250mhz"; > - linux,phandle = <0x5>; > - phandle = <0x5>; > - }; > - > - clk250mhz_1 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <250000000>; > - clock-output-names = "xgmacclk0_ptp_250mhz"; > - linux,phandle = <0x6>; > - phandle = <0x6>; > - }; > - > - clk250mhz_2 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <250000000>; > - clock-output-names = "xgmacclk1_dma_250mhz"; > - linux,phandle = <0x7>; > - phandle = <0x7>; > - }; > - > - clk250mhz_3 { > - compatible = "fixed-clock"; > - #clock-cells = <0x0>; > - clock-frequency = <250000000>; > - clock-output-names = "xgmacclk1_ptp_250mhz"; > - linux,phandle = <0x8>; > - phandle = <0x8>; > - }; > - > - phy@e1240800 { > - status = "disabled"; > - compatible = "amd,xgbe-phy-seattle-v1a"; > - reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ > - <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ > - <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ > - interrupts = <0x0 0x143 0x4>; > - amd,speed-set = <0x0>; > - amd,serdes-blwc = <0x1 0x1 0x0>; > - amd,serdes-cdr-rate = <0x2 0x2 0x7>; > - amd,serdes-pq-skew = <0xa 0xa 0x12>; > - amd,serdes-tx-amp = <0xf 0xf 0xa>; > - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; > - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; > - linux,phandle = <0x9>; > - phandle = <0x9>; > - }; > - > - phy@e1240c00 { > - status = "disabled"; > - compatible = "amd,xgbe-phy-seattle-v1a"; > - reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ > - <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ > - <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ > - interrupts = <0x0 0x142 0x4>; > - amd,speed-set = <0x0>; > - amd,serdes-blwc = <0x1 0x1 0x0>; > - amd,serdes-cdr-rate = <0x2 0x2 0x7>; > - amd,serdes-pq-skew = <0xa 0xa 0x12>; > - amd,serdes-tx-amp = <0xf 0xf 0xa>; > - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; > - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; > - linux,phandle = <0xa>; > - phandle = <0xa>; > - }; > - > - xgmac0_smmu: smmu@e0600000 { > - compatible = "arm,mmu-401"; > - reg = <0 0xe0600000 0 0x10000>; > - #global-interrupts = <1>; > - interrupts = /* Uses combined intr for both > - * global and context > - */ > - <0 336 4>, > - <0 336 4>; > - #iommu-cells = <2>; > - dma-coherent; > - }; > - > - xgmac1_smmu: smmu@e0800000 { > - compatible = "arm,mmu-401"; > - reg = <0 0xe0800000 0 0x10000>; > - #global-interrupts = <1>; > - interrupts = /* Uses combined intr for both > - * global and context > - */ > - <0 335 4>, > - <0 335 4>; > - #iommu-cells = <2>; > - dma-coherent; > - }; > - > - xgmac@e0700000 { > - status = "disabled"; > - compatible = "amd,xgbe-seattle-v1a"; > - reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; > - interrupts = <0x0 0x145 0x4>, > - <0x0 0x15a 0x1>, > - <0x0 0x15b 0x1>, > - <0x0 0x15c 0x1>, > - <0x0 0x15d 0x1>; > - amd,per-channel-interrupt; > - mac-address = [02 a1 a2 a3 a4 a5]; > - clocks = <0x5 0x6>; > - clock-names = "dma_clk", "ptp_clk"; > - phy-handle = <0x9>; > - phy-mode = "xgmii"; > - dma-coherent; > - iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ > - linux,phandle = <0xb>; > - phandle = <0xb>; > - }; > - > - xgmac@e0900000 { > - status = "disabled"; > - compatible = "amd,xgbe-seattle-v1a"; > - reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; > - interrupts = <0x0 0x144 0x4>, > - <0x0 0x155 0x1>, > - <0x0 0x156 0x1>, > - <0x0 0x157 0x1>, > - <0x0 0x158 0x1>; > - amd,per-channel-interrupt; > - mac-address = [02 b1 b2 b3 b4 b5]; > - clocks = <0x7 0x8>; > - clock-names = "dma_clk", "ptp_clk"; > - phy-handle = <0xa>; > - phy-mode = "xgmii"; > - dma-coherent; > - iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ > - linux,phandle = <0xc>; > - phandle = <0xc>; > - }; > - }; > - > - chosen { > - stdout-path = "/smb/serial@e1010000"; > - /* Note: > - * Linux support for pci-probe-only DT is not > - * stable. Disable this for now and let Linux > - * take care of the resource assignment. > - */ > - // linux,pci-probe-only; > - }; > - > - psci { > - compatible = "arm,psci-0.2", "arm,psci"; > - method = "smc"; > - }; > + model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; > + compatible = "amd,seattle-overdrive", "amd,seattle"; > + interrupt-parent = <&gic>; > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + > + gic: interrupt-controller@e1101000 { > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <0x3>; > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + reg = <0x0 0xe1110000 0x0 0x1000>, > + <0x0 0xe112f000 0x0 0x2000>, > + <0x0 0xe1140000 0x0 0x2000>, > + <0x0 0xe1160000 0x0 0x2000>; > + interrupts = <GIC_PPI 0x9 (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(4))>; > + ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; > + > + msi: v2m@e0080000 { > + compatible = "arm,gic-v2m-frame"; > + reg = <0x0 0x80000 0x0 0x1000>; > + msi-controller; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 0xd (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, > + <GIC_PPI 0xe (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, > + <GIC_PPI 0xb (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, > + <GIC_PPI 0xa (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>; > + }; > + > + smb { > + compatible = "simple-bus"; > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + ranges; > + /* > + * dma-ranges is 40-bit address space containing: > + * - GICv2m MSI register is at 0xe0080000 > + * - DRAM range [0x8000000000 to 0xffffffffff] > + */ > + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; > + > + adl3clk: clk100mhz_0 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <100000000>; > + clock-output-names = "adl3clk_100mhz"; > + }; > + > + ccpclk: clk375mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <375000000>; > + clock-output-names = "ccpclk_375mhz"; > + }; > + > + sataclk: clk333mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <333000000>; > + clock-output-names = "sataclk_333mhz"; > + }; > + > + pcieclk: clk500mhz_0 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <500000000>; > + clock-output-names = "pcieclk_500mhz"; > + }; > + > + dmaclk: clk500mhz_1 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <500000000>; > + clock-output-names = "dmaclk_500mhz"; > + }; > + > + miscclk: clk250mhz_4 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <250000000>; > + clock-output-names = "miscclk_250mhz"; > + }; > + > + uartspiclk: clk100mhz_1 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <100000000>; > + clock-output-names = "uartspiclk_100mhz"; > + }; > + > + sata0_smmu: smmu@e0200000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0200000 0 0x10000>; > + > + /* Uses combined intr for both global and context */ > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <2>; > + dma-coherent; > + }; > + > + sata1_smmu: smmu@e0c00000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0c00000 0 0x10000>; > + > + /* Uses combined intr for both global and context */ > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <2>; > + dma-coherent; > + }; > + > + sata@e0300000 { > + compatible = "snps,dwc-ahci"; > + reg = <0x0 0xe0300000 0x0 0xf0000>; > + interrupts = <GIC_SPI 0x163 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sataclk>; > + dma-coherent; > + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ > + }; > + > + sata@e0d00000 { > + status = "disabled"; > + compatible = "snps,dwc-ahci"; > + reg = <0x0 0xe0d00000 0x0 0xf0000>; > + interrupts = <GIC_SPI 0x162 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sataclk>; > + dma-coherent; > + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ > + }; > + > + i2c@e1000000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0xe1000000 0x0 0x1000>; > + interrupts = <GIC_SPI 0x165 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&miscclk>; > + }; > + > + i2c@e0050000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0xe0050000 0x0 0x1000>; > + interrupts = <GIC_SPI 0x154 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&miscclk>; > + }; > + > + serial@e1010000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0xe1010000 0x0 0x1000>; > + interrupts = <GIC_SPI 0x148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk &uartspiclk>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + ssp@e1020000 { > + compatible = "arm,pl022", "arm,primecell"; > + reg = <0x0 0xe1020000 0x0 0x1000>; > + spi-controller; > + interrupts = <GIC_SPI 0x14a IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + }; > + > + ssp@e1030000 { > + compatible = "arm,pl022", "arm,primecell"; > + reg = <0x0 0xe1030000 0x0 0x1000>; > + spi-controller; > + interrupts = <GIC_SPI 0x149 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + num-cs = <0x1>; > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + > + sdcard@0 { > + compatible = "mmc-spi-slot"; > + reg = <0x0>; > + spi-max-frequency = <20000000>; > + voltage-ranges = <3200 3400>; > + pl022,hierarchy = <0x0>; > + pl022,interface = <0x0>; > + pl022,com-mode = <0x0>; > + pl022,rx-level-trig = <0x0>; > + pl022,tx-level-trig = <0x0>; > + }; > + }; > + > + gpio@e1050000 { /* [0 : 7] */ > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <0x2>; > + reg = <0x0 0xe1050000 0x0 0x1000>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <0x2>; > + interrupts = <GIC_SPI 0x166 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + }; > + > + gpio@e0020000 { /* [8 : 15] */ > + status = "disabled"; > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <0x2>; > + reg = <0x0 0xe0020000 0x0 0x1000>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <0x2>; > + interrupts = <GIC_SPI 0x16e IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + }; > + > + gpio@e0030000 { /* [16 : 23] */ > + status = "disabled"; > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <0x2>; > + reg = <0x0 0xe0030000 0x0 0x1000>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <0x2>; > + interrupts = <GIC_SPI 0x16d IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + }; > + > + gpio@e0080000 { /* [24] */ > + compatible = "arm,pl061", "arm,primecell"; > + #gpio-cells = <0x2>; > + reg = <0x0 0xe0080000 0x0 0x1000>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <0x2>; > + interrupts = <GIC_SPI 0x169 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartspiclk>; > + clock-names = "apb_pclk"; > + }; > + > + ccp: ccp@e0100000 { > + compatible = "amd,ccp-seattle-v1a"; > + reg = <0x0 0xe0100000 0x0 0x10000>; > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > + dma-coherent; > + amd,zlib-support = <0x1>; > + }; > + > + pcie: pcie@f0000000 { > + compatible = "pci-host-ecam-generic"; > + #address-cells = <0x3>; > + #size-cells = <0x2>; > + #interrupt-cells = <0x1>; > + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; > + device_type = "pci"; > + bus-range = <0x0 0x7f>; > + msi-parent = <&msi>; > + reg = <0x0 0xf0000000 0x0 0x10000000>; > + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; > + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>, > + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>, > + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>, > + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>, > + > + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>, > + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>, > + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>, > + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>, > + > + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>, > + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>, > + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>, > + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>; > + dma-coherent; > + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; > + ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ > + <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ > + <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ > + }; > + > + pcie_smmu: smmu@e0a00000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0a00000 0 0x10000>; > + > + /* Uses combined intr for both global and context */ > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <1>; > + dma-coherent; > + }; > + > + ccn@0xe8000000 { > + compatible = "arm,ccn-504"; > + reg = <0x0 0xe8000000 0x0 0x1000000>; > + interrupts = <GIC_SPI 0x17c IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + gwdt@e0bb0000 { > + status = "disabled"; > + compatible = "arm,sbsa-gwdt"; > + reg = <0x0 0xe0bb0000 0x0 0x10000 > + 0x0 0xe0bc0000 0x0 0x10000>; > + reg-names = "refresh", "control"; > + interrupts = <GIC_SPI 0x151 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ws0"; > + }; > + > + kcs@e0010000 { > + status = "disabled"; > + compatible = "ipmi-kcs"; > + device_type = "ipmi"; > + reg = <0x0 0xe0010000 0 0x8>; > + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ipmi_kcs"; > + reg-size = <1>; > + reg-spacing = <4>; > + }; > + > + xgmacclk0_dma: clk250mhz_0 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <250000000>; > + clock-output-names = "xgmacclk0_dma_250mhz"; > + }; > + > + xgmacclk0_ptp: clk250mhz_1 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <250000000>; > + clock-output-names = "xgmacclk0_ptp_250mhz"; > + }; > + > + xgmacclk1_dma: clk250mhz_2 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <250000000>; > + clock-output-names = "xgmacclk1_dma_250mhz"; > + }; > + > + xgmacclk1_ptp: clk250mhz_3 { > + compatible = "fixed-clock"; > + #clock-cells = <0x0>; > + clock-frequency = <250000000>; > + clock-output-names = "xgmacclk1_ptp_250mhz"; > + }; > + > + xgmac0_phy: phy@e1240800 { > + compatible = "amd,xgbe-phy-seattle-v1a"; > + reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ > + <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ > + <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ > + interrupts = <GIC_SPI 0x143 IRQ_TYPE_LEVEL_HIGH>; > + amd,speed-set = <0x0>; > + amd,serdes-blwc = <0x1 0x1 0x0>; > + amd,serdes-cdr-rate = <0x2 0x2 0x7>; > + amd,serdes-pq-skew = <0xa 0xa 0x12>; > + amd,serdes-tx-amp = <0xf 0xf 0xa>; > + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; > + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; > + status = "disabled"; > + }; > + > + xgmac1_phy: phy@e1240c00 { > + compatible = "amd,xgbe-phy-seattle-v1a"; > + reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ > + <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ > + <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ > + interrupts = <GIC_SPI 0x142 IRQ_TYPE_LEVEL_HIGH>; > + amd,speed-set = <0x0>; > + amd,serdes-blwc = <0x1 0x1 0x0>; > + amd,serdes-cdr-rate = <0x2 0x2 0x7>; > + amd,serdes-pq-skew = <0xa 0xa 0x12>; > + amd,serdes-tx-amp = <0xf 0xf 0xa>; > + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; > + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; > + status = "disabled"; > + }; > + > + xgmac0_smmu: smmu@e0600000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0600000 0 0x10000>; > + > + /* Uses combined intr for both global and context */ > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <2>; > + dma-coherent; > + }; > + > + xgmac1_smmu: smmu@e0800000 { > + compatible = "arm,mmu-401"; > + reg = <0 0xe0800000 0 0x10000>; > + > + /* Uses combined intr for both global and context */ > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <2>; > + dma-coherent; > + }; > + > + xgmac@e0700000 { > + compatible = "amd,xgbe-seattle-v1a"; > + reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; > + interrupts = <GIC_SPI 0x145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0x15a IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x15b IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x15c IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x15d IRQ_TYPE_EDGE_RISING>; > + amd,per-channel-interrupt; > + mac-address = [02 a1 a2 a3 a4 a5]; > + clocks = <&xgmacclk0_dma &xgmacclk0_ptp>; > + clock-names = "dma_clk", "ptp_clk"; > + phy-handle = <&xgmac0_phy>; > + phy-mode = "xgmii"; > + > + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ > + dma-coherent; > + status = "disabled"; > + }; > + > + xgmac@e0900000 { > + compatible = "amd,xgbe-seattle-v1a"; > + reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; > + interrupts = <GIC_SPI 0x144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0x155 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x156 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x157 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 0x158 IRQ_TYPE_EDGE_RISING>; > + amd,per-channel-interrupt; > + mac-address = [02 b1 b2 b3 b4 b5]; > + clocks = <&xgmacclk1_dma &xgmacclk1_ptp>; > + clock-names = "dma_clk", "ptp_clk"; > + phy-handle = <&xgmac1_phy>; > + phy-mode = "xgmii"; > + > + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ > + dma-coherent; > + status = "disabled"; > + }; > + }; > + > + chosen { > + stdout-path = "/smb/serial@e1010000"; > + }; > + > + psci { > + compatible = "arm,psci-0.2", "arm,psci"; > + method = "smc"; > + }; > }; > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 1 September 2017 at 12:12, Leif Lindholm <leif.lindholm@linaro.org> wrote: > Adding Grant, > > On Thu, Aug 31, 2017 at 02:08:28PM +0100, Ard Biesheuvel wrote: >> Clean up the device tree source file, by switching to Tianocore >> conventions for line endings and whitespace etc, and by replacing >> open coded values with symbol constants and/or phandle references. > > 1: All for the getting rid of open coding. > > 2: As for the line endings/whitespace, I am less convinced. > > It is its own (and very specific) file format, it is not > edk2-specific, and just like (GNU)Makefiles and shellscripts they > originated in a CR-free environment. > Yeah, that's a good point actually. Ideally, we'd just import this mythical, separate DT repository that is disjoint from the kernel entirely. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On Fri, Sep 01, 2017 at 12:14:53PM +0100, Ard Biesheuvel wrote: > On 1 September 2017 at 12:12, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > Adding Grant, > > > > On Thu, Aug 31, 2017 at 02:08:28PM +0100, Ard Biesheuvel wrote: > >> Clean up the device tree source file, by switching to Tianocore > >> conventions for line endings and whitespace etc, and by replacing > >> open coded values with symbol constants and/or phandle references. > > > > 1: All for the getting rid of open coding. > > > > 2: As for the line endings/whitespace, I am less convinced. > > > > It is its own (and very specific) file format, it is not > > edk2-specific, and just like (GNU)Makefiles and shellscripts they > > originated in a CR-free environment. > > Yeah, that's a good point actually. Ideally, we'd just import this > mythical, separate DT repository that is disjoint from the kernel > entirely. That was the subtext, yes :) / Leif _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 1 September 2017 at 12:17, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Fri, Sep 01, 2017 at 12:14:53PM +0100, Ard Biesheuvel wrote: >> On 1 September 2017 at 12:12, Leif Lindholm <leif.lindholm@linaro.org> wrote: >> > Adding Grant, >> > >> > On Thu, Aug 31, 2017 at 02:08:28PM +0100, Ard Biesheuvel wrote: >> >> Clean up the device tree source file, by switching to Tianocore >> >> conventions for line endings and whitespace etc, and by replacing >> >> open coded values with symbol constants and/or phandle references. >> > >> > 1: All for the getting rid of open coding. >> > >> > 2: As for the line endings/whitespace, I am less convinced. >> > >> > It is its own (and very specific) file format, it is not >> > edk2-specific, and just like (GNU)Makefiles and shellscripts they >> > originated in a CR-free environment. >> >> Yeah, that's a good point actually. Ideally, we'd just import this >> mythical, separate DT repository that is disjoint from the kernel >> entirely. > > That was the subtext, yes :) > I should note that the only other public AMD Seattle DT is in the kernel tree, and it is slightly out of date afaik. I proposed updates in the past, but nobody seems to care _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts index 4039f666004a..81477fe43cdd 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts @@ -2,6 +2,7 @@ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board * * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * Copyright 2015 - 2017 Linaro, Ltd. All Rights Reserved. * * This program and the accompanying materials are licensed and made available * under the terms and conditions of the BSD License which accompanies this @@ -14,497 +15,473 @@ * */ +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GIC_CPU_MASK(num) (((1 << (num)) - 1) << 8) + /dts-v1/; / { - model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - interrupt-parent = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x2>; - - interrupt-controller@e1101000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <0x3>; - #address-cells = <0x2>; - #size-cells = <0x2>; - reg = <0x0 0xe1110000 0x0 0x1000>, - <0x0 0xe112f000 0x0 0x2000>, - <0x0 0xe1140000 0x0 0x2000>, - <0x0 0xe1160000 0x0 0x2000>; - interrupts = <0x1 0x9 0xf04>; - ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; - linux,phandle = <0x1>; - phandle = <0x1>; - - v2m@e0080000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0x0 0x1000>; - linux,phandle = <0x4>; - phandle = <0x4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <0x1 0xd 0xff04>, - <0x1 0xe 0xff04>, - <0x1 0xb 0xff04>, - <0x1 0xa 0xff04>; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <0x2>; - #size-cells = <0x2>; - ranges; - /* - * dma-ranges is 40-bit address space containing: - * - GICv2m MSI register is at 0xe0080000 - * - DRAM range [0x8000000000 to 0xffffffffff] - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - clk100mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - clk375mhz { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - clk333mhz { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <333000000>; - clock-output-names = "sataclk_333mhz"; - linux,phandle = <0x2>; - phandle = <0x2>; - }; - - clk500mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - clk250mhz_4 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "miscclk_250mhz"; - linux,phandle = <0xd>; - phandle = <0xd>; - }; - - clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - linux,phandle = <0x3>; - phandle = <0x3>; - }; - - sata0_smmu: smmu@e0200000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0200000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 332 4>, - <0 332 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - sata1_smmu: smmu@e0c00000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0c00000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 331 4>, - <0 331 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - sata@e0300000 { - compatible = "snps,dwc-ahci"; - reg = <0x0 0xe0300000 0x0 0xf0000>; - interrupts = <0x0 0x163 0x4>; - clocks = <0x2>; - dma-coherent; - iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ - }; - - sata@e0d00000 { - status = "disabled"; - compatible = "snps,dwc-ahci"; - reg = <0x0 0xe0d00000 0x0 0xf0000>; - interrupts = <0x0 0x162 0x4>; - clocks = <0x2>; - dma-coherent; - iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ - }; - - i2c@e1000000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xe1000000 0x0 0x1000>; - interrupts = <0x0 0x165 0x4>; - clocks = <0xd>; - }; - - i2c@e0050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xe0050000 0x0 0x1000>; - interrupts = <0x0 0x154 0x4>; - clocks = <0xd>; - }; - - serial@e1010000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xe1010000 0x0 0x1000>; - interrupts = <0x0 0x148 0x4>; - clocks = <0x3 0x3>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp@e1020000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xe1020000 0x0 0x1000>; - spi-controller; - interrupts = <0x0 0x14a 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - ssp@e1030000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xe1030000 0x0 0x1000>; - spi-controller; - interrupts = <0x0 0x149 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - num-cs = <0x1>; - #address-cells = <0x1>; - #size-cells = <0x0>; - - sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0x0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0x0>; - pl022,interface = <0x0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0x0>; - pl022,tx-level-trig = <0x0>; - }; - }; - - gpio@e1050000 { /* [0 : 7] */ - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe1050000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x166 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0020000 { /* [8 : 15] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0020000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x16e 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0030000 { /* [16 : 23] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0030000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x16d 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - gpio@e0080000 { /* [24] */ - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <0x2>; - reg = <0x0 0xe0080000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <0x2>; - interrupts = <0x0 0x169 0x4>; - clocks = <0x3>; - clock-names = "apb_pclk"; - }; - - ccp: ccp@e0100000 { - compatible = "amd,ccp-seattle-v1a"; - reg = <0x0 0xe0100000 0x0 0x10000>; - interrupts = <0x0 0x3 0x4>; - dma-coherent; - amd,zlib-support = <0x1>; - }; - - pcie: pcie@f0000000 { - compatible = "pci-host-ecam-generic"; - #address-cells = <0x3>; - #size-cells = <0x2>; - #interrupt-cells = <0x1>; - iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; - device_type = "pci"; - bus-range = <0x0 0x7f>; - msi-parent = <0x4>; - reg = <0x0 0xf0000000 0x0 0x10000000>; - interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, - <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, - <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, - <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, - - <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, - <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, - <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, - <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, - - <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, - <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, - <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, - <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; - dma-coherent; - dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; - ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ - <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ - <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ - }; - - pcie_smmu: smmu@e0a00000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0a00000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 333 4>, - <0 333 4>; - #iommu-cells = <1>; - dma-coherent; - }; - - ccn@0xe8000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0xe8000000 0x0 0x1000000>; - interrupts = <0x0 0x17c 0x4>; - }; - - gwdt@e0bb0000 { - status = "disabled"; - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0xe0bb0000 0x0 0x10000 - 0x0 0xe0bc0000 0x0 0x10000>; - reg-names = "refresh", "control"; - interrupts = <0x0 0x151 0x4>; - interrupt-names = "ws0"; - }; - - kcs@e0010000 { - status = "disabled"; - compatible = "ipmi-kcs"; - device_type = "ipmi"; - reg = <0x0 0xe0010000 0 0x8>; - interrupts = <0 389 4>; - interrupt-names = "ipmi_kcs"; - reg-size = <1>; - reg-spacing = <4>; - }; - - clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - linux,phandle = <0x5>; - phandle = <0x5>; - }; - - clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - linux,phandle = <0x6>; - phandle = <0x6>; - }; - - clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - linux,phandle = <0x7>; - phandle = <0x7>; - }; - - clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - linux,phandle = <0x8>; - phandle = <0x8>; - }; - - phy@e1240800 { - status = "disabled"; - compatible = "amd,xgbe-phy-seattle-v1a"; - reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts = <0x0 0x143 0x4>; - amd,speed-set = <0x0>; - amd,serdes-blwc = <0x1 0x1 0x0>; - amd,serdes-cdr-rate = <0x2 0x2 0x7>; - amd,serdes-pq-skew = <0xa 0xa 0x12>; - amd,serdes-tx-amp = <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0x9>; - phandle = <0x9>; - }; - - phy@e1240c00 { - status = "disabled"; - compatible = "amd,xgbe-phy-seattle-v1a"; - reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts = <0x0 0x142 0x4>; - amd,speed-set = <0x0>; - amd,serdes-blwc = <0x1 0x1 0x0>; - amd,serdes-cdr-rate = <0x2 0x2 0x7>; - amd,serdes-pq-skew = <0xa 0xa 0x12>; - amd,serdes-tx-amp = <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0xa>; - phandle = <0xa>; - }; - - xgmac0_smmu: smmu@e0600000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0600000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - xgmac1_smmu: smmu@e0800000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0800000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - xgmac@e0700000 { - status = "disabled"; - compatible = "amd,xgbe-seattle-v1a"; - reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; - interrupts = <0x0 0x145 0x4>, - <0x0 0x15a 0x1>, - <0x0 0x15b 0x1>, - <0x0 0x15c 0x1>, - <0x0 0x15d 0x1>; - amd,per-channel-interrupt; - mac-address = [02 a1 a2 a3 a4 a5]; - clocks = <0x5 0x6>; - clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0x9>; - phy-mode = "xgmii"; - dma-coherent; - iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xb>; - phandle = <0xb>; - }; - - xgmac@e0900000 { - status = "disabled"; - compatible = "amd,xgbe-seattle-v1a"; - reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; - interrupts = <0x0 0x144 0x4>, - <0x0 0x155 0x1>, - <0x0 0x156 0x1>, - <0x0 0x157 0x1>, - <0x0 0x158 0x1>; - amd,per-channel-interrupt; - mac-address = [02 b1 b2 b3 b4 b5]; - clocks = <0x7 0x8>; - clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0xa>; - phy-mode = "xgmii"; - dma-coherent; - iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xc>; - phandle = <0xc>; - }; - }; - - chosen { - stdout-path = "/smb/serial@e1010000"; - /* Note: - * Linux support for pci-probe-only DT is not - * stable. Disable this for now and let Linux - * take care of the resource assignment. - */ - // linux,pci-probe-only; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - }; + model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; + compatible = "amd,seattle-overdrive", "amd,seattle"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + gic: interrupt-controller@e1101000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0xe1110000 0x0 0x1000>, + <0x0 0xe112f000 0x0 0x2000>, + <0x0 0xe1140000 0x0 0x2000>, + <0x0 0xe1160000 0x0 0x2000>; + interrupts = <GIC_PPI 0x9 (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(4))>; + ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; + + msi: v2m@e0080000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x80000 0x0 0x1000>; + msi-controller; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 0xd (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, + <GIC_PPI 0xe (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, + <GIC_PPI 0xb (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>, + <GIC_PPI 0xa (IRQ_TYPE_LEVEL_HIGH | GIC_CPU_MASK(8))>; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + adl3clk: clk100mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "adl3clk_100mhz"; + }; + + ccpclk: clk375mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <375000000>; + clock-output-names = "ccpclk_375mhz"; + }; + + sataclk: clk333mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <333000000>; + clock-output-names = "sataclk_333mhz"; + }; + + pcieclk: clk500mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "pcieclk_500mhz"; + }; + + dmaclk: clk500mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "dmaclk_500mhz"; + }; + + miscclk: clk250mhz_4 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "miscclk_250mhz"; + }; + + uartspiclk: clk100mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "uartspiclk_100mhz"; + }; + + sata0_smmu: smmu@e0200000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0200000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0c00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <2>; + dma-coherent; + }; + + sata@e0300000 { + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0300000 0x0 0xf0000>; + interrupts = <GIC_SPI 0x163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sataclk>; + dma-coherent; + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ + }; + + sata@e0d00000 { + status = "disabled"; + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0d00000 0x0 0xf0000>; + interrupts = <GIC_SPI 0x162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sataclk>; + dma-coherent; + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ + }; + + i2c@e1000000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe1000000 0x0 0x1000>; + interrupts = <GIC_SPI 0x165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&miscclk>; + }; + + i2c@e0050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe0050000 0x0 0x1000>; + interrupts = <GIC_SPI 0x154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&miscclk>; + }; + + serial@e1010000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xe1010000 0x0 0x1000>; + interrupts = <GIC_SPI 0x148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk &uartspiclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@e1020000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1020000 0x0 0x1000>; + spi-controller; + interrupts = <GIC_SPI 0x14a IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + ssp@e1030000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1030000 0x0 0x1000>; + spi-controller; + interrupts = <GIC_SPI 0x149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + num-cs = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sdcard@0 { + compatible = "mmc-spi-slot"; + reg = <0x0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3200 3400>; + pl022,hierarchy = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + pl022,rx-level-trig = <0x0>; + pl022,tx-level-trig = <0x0>; + }; + }; + + gpio@e1050000 { /* [0 : 7] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe1050000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <GIC_SPI 0x166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0020000 { /* [8 : 15] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0020000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <GIC_SPI 0x16e IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0030000 { /* [16 : 23] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0030000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <GIC_SPI 0x16d IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + gpio@e0080000 { /* [24] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0080000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <GIC_SPI 0x169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartspiclk>; + clock-names = "apb_pclk"; + }; + + ccp: ccp@e0100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0x0 0xe0100000 0x0 0x10000>; + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + amd,zlib-support = <0x1>; + }; + + pcie: pcie@f0000000 { + compatible = "pci-host-ecam-generic"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; + device_type = "pci"; + bus-range = <0x0 0x7f>; + msi-parent = <&msi>; + reg = <0x0 0xf0000000 0x0 0x10000000>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>; + dma-coherent; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; + ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ + <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ + <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ + }; + + pcie_smmu: smmu@e0a00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0a00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + dma-coherent; + }; + + ccn@0xe8000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0xe8000000 0x0 0x1000000>; + interrupts = <GIC_SPI 0x17c IRQ_TYPE_LEVEL_HIGH>; + }; + + gwdt@e0bb0000 { + status = "disabled"; + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0xe0bb0000 0x0 0x10000 + 0x0 0xe0bc0000 0x0 0x10000>; + reg-names = "refresh", "control"; + interrupts = <GIC_SPI 0x151 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ws0"; + }; + + kcs@e0010000 { + status = "disabled"; + compatible = "ipmi-kcs"; + device_type = "ipmi"; + reg = <0x0 0xe0010000 0 0x8>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ipmi_kcs"; + reg-size = <1>; + reg-spacing = <4>; + }; + + xgmacclk0_dma: clk250mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_dma_250mhz"; + }; + + xgmacclk0_ptp: clk250mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_ptp_250mhz"; + }; + + xgmacclk1_dma: clk250mhz_2 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_dma_250mhz"; + }; + + xgmacclk1_ptp: clk250mhz_3 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_ptp_250mhz"; + }; + + xgmac0_phy: phy@e1240800 { + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = <GIC_SPI 0x143 IRQ_TYPE_LEVEL_HIGH>; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + status = "disabled"; + }; + + xgmac1_phy: phy@e1240c00 { + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = <GIC_SPI 0x142 IRQ_TYPE_LEVEL_HIGH>; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + status = "disabled"; + }; + + xgmac0_smmu: smmu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts = <1>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac@e0700000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; + interrupts = <GIC_SPI 0x145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x15a IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x15b IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x15c IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x15d IRQ_TYPE_EDGE_RISING>; + amd,per-channel-interrupt; + mac-address = [02 a1 a2 a3 a4 a5]; + clocks = <&xgmacclk0_dma &xgmacclk0_ptp>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <&xgmac0_phy>; + phy-mode = "xgmii"; + + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status = "disabled"; + }; + + xgmac@e0900000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; + interrupts = <GIC_SPI 0x144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x155 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x156 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 0x158 IRQ_TYPE_EDGE_RISING>; + amd,per-channel-interrupt; + mac-address = [02 b1 b2 b3 b4 b5]; + clocks = <&xgmacclk1_dma &xgmacclk1_ptp>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <&xgmac1_phy>; + phy-mode = "xgmii"; + + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status = "disabled"; + }; + }; + + chosen { + stdout-path = "/smb/serial@e1010000"; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + }; };
Clean up the device tree source file, by switching to Tianocore conventions for line endings and whitespace etc, and by replacing open coded values with symbol constants and/or phandle references. The resulting .dtb will likely not be identical at the bit level, but the modifications are cosmetic only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 957 ++++++++++---------- 1 file changed, 467 insertions(+), 490 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel