diff mbox series

[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)

Message ID 878tckpwuw.fsf@linaro.org
State Accepted
Commit 9a1b9cb4d6fcf88d68f55b97c7d9d09c5606fed7
Headers show
Series [AArch64] Tighten aarch64_secondary_reload condition (PR 83845) | expand

Commit Message

Richard Sandiford Jan. 26, 2018, 1:34 p.m. UTC 
aarch64_secondary_reload enforced a secondary reload via
aarch64_sve_reload_be for memory and pseudo registers, but failed
to do the same for subregs of pseudo registers.  To avoid this and
any similar problems, the patch instead tests for things that the move
patterns handle directly; if the operand isn't one of those, we should
use the reload pattern instead.

The patch fixes an ICE in sve/mask_struct_store_3.c for aarch64_be,
where the bogus target description was (rightly) causing LRA to cycle.

Tested on aarch64_be-elf and aarch64-linux-gnu.  OK to install?

Richard


2018-01-26  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	PR tearget/83845
	* config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten
	check for operands that need to go through aarch64_sve_reload_be.

Comments

James Greenhalgh Feb. 1, 2018, 10:55 a.m. UTC | #1 
On Fri, Jan 26, 2018 at 01:34:31PM +0000, Richard Sandiford wrote:
> aarch64_secondary_reload enforced a secondary reload via

> aarch64_sve_reload_be for memory and pseudo registers, but failed

> to do the same for subregs of pseudo registers.  To avoid this and

> any similar problems, the patch instead tests for things that the move

> patterns handle directly; if the operand isn't one of those, we should

> use the reload pattern instead.

> 

> The patch fixes an ICE in sve/mask_struct_store_3.c for aarch64_be,

> where the bogus target description was (rightly) causing LRA to cycle.

> 

> Tested on aarch64_be-elf and aarch64-linux-gnu.  OK to install?


OK.

Thanks,
James

> 

> Richard

> 

> 

> 2018-01-26  Richard Sandiford  <richard.sandiford@linaro.org>

> 

> gcc/

> 	PR tearget/83845

> 	* config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten

> 	check for operands that need to go through aarch64_sve_reload_be.

        sri->icode = CODE_FOR_aarch64_sve_reload_be;
diff mbox series

Patch

Index: gcc/config/aarch64/aarch64.c
===================================================================
--- gcc/config/aarch64/aarch64.c	2018-01-19 11:57:11.141991997 +0000
+++ gcc/config/aarch64/aarch64.c	2018-01-26 13:32:54.240529011 +0000
@@ -7249,9 +7249,14 @@  aarch64_secondary_reload (bool in_p ATTR
 			  machine_mode mode,
 			  secondary_reload_info *sri)
 {
+  /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
+     directly by the *aarch64_sve_mov<mode>_be move pattern.  See the
+     comment at the head of aarch64-sve.md for more details about the
+     big-endian handling.  */
   if (BYTES_BIG_ENDIAN
       && reg_class_subset_p (rclass, FP_REGS)
-      && (MEM_P (x) || (REG_P (x) && !HARD_REGISTER_P (x)))
+      && !((REG_P (x) && HARD_REGISTER_P (x))
+	   || aarch64_simd_valid_immediate (x, NULL))
       && aarch64_sve_data_mode_p (mode))
     {
       sri->icode = CODE_FOR_aarch64_sve_reload_be;