[v2,41/67] target/arm: Implement FDUP/DUP

Message ID	20180217182323.25885-42-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 10:22:57 -0800 Message-Id: <20180217182323.25885-42-richard.henderson@linaro.org> In-Reply-To: <20180217182323.25885-1-richard.henderson@linaro.org> References: <20180217182323.25885-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP Precedence: list Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Scalable Vector Extension \| expand [v2,00/67] target/arm: Scalable Vector Extension [v2,01/67] target/arm: Enable SVE for aarch64-linux-user [v2,02/67] target/arm: Introduce translate-a64.h [v2,03/67] target/arm: Add SVE decode skeleton [v2,04/67] target/arm: Implement SVE Bitwise Logical - Unpredicated Group [v2,05/67] target/arm: Implement SVE load vector/predicate [v2,06/67] target/arm: Implement SVE predicate test [v2,07/67] target/arm: Implement SVE Predicate Logical Operations Group [v2,08/67] target/arm: Implement SVE Predicate Misc Group [v2,09/67] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group [v2,10/67] target/arm: Implement SVE Integer Reduction Group [v2,11/67] target/arm: Implement SVE bitwise shift by immediate (predicated) [v2,12/67] target/arm: Implement SVE bitwise shift by vector (predicated) [v2,13/67] target/arm: Implement SVE bitwise shift by wide elements (predicated) [v2,14/67] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group [v2,15/67] target/arm: Implement SVE Integer Multiply-Add Group [v2,16/67] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group [v2,17/67] target/arm: Implement SVE Index Generation Group [v2,18/67] target/arm: Implement SVE Stack Allocation Group [v2,19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group [v2,20/67] target/arm: Implement SVE Compute Vector Address Group [v2,21/67] target/arm: Implement SVE floating-point exponential accelerator [v2,22/67] target/arm: Implement SVE floating-point trig select coefficient [v2,23/67] target/arm: Implement SVE Element Count Group [v2,24/67] target/arm: Implement SVE Bitwise Immediate Group [v2,25/67] target/arm: Implement SVE Integer Wide Immediate - Predicated Group [v2,26/67] target/arm: Implement SVE Permute - Extract Group [v2,27/67] target/arm: Implement SVE Permute - Unpredicated Group [v2,28/67] target/arm: Implement SVE Permute - Predicates Group [v2,29/67] target/arm: Implement SVE Permute - Interleaving Group [v2,30/67] target/arm: Implement SVE compress active elements [v2,31/67] target/arm: Implement SVE conditionally broadcast/extract element [v2,32/67] target/arm: Implement SVE copy to vector (predicated) [v2,33/67] target/arm: Implement SVE reverse within elements [v2,34/67] target/arm: Implement SVE vector splice (predicated) [v2,35/67] target/arm: Implement SVE Select Vectors Group [v2,36/67] target/arm: Implement SVE Integer Compare - Vectors Group [v2,37/67] target/arm: Implement SVE Integer Compare - Immediate Group [v2,38/67] target/arm: Implement SVE Partition Break Group [v2,39/67] target/arm: Implement SVE Predicate Count Group [v2,40/67] target/arm: Implement SVE Integer Compare - Scalars Group [v2,41/67] target/arm: Implement FDUP/DUP [v2,42/67] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group [v2,43/67] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group [v2,44/67] target/arm: Implement SVE Memory Contiguous Load Group [v2,45/67] target/arm: Implement SVE Memory Contiguous Store Group [v2,46/67] target/arm: Implement SVE load and broadcast quadword [v2,47/67] target/arm: Implement SVE integer convert to floating-point [v2,48/67] target/arm: Implement SVE floating-point arithmetic (predicated) [v2,49/67] target/arm: Implement SVE FP Multiply-Add Group [v2,50/67] target/arm: Implement SVE Floating Point Accumulating Reduction Group [v2,51/67] target/arm: Implement SVE load and broadcast element [v2,52/67] target/arm: Implement SVE store vector/predicate register [v2,53/67] target/arm: Implement SVE scatter stores [v2,54/67] target/arm: Implement SVE prefetches [v2,55/67] target/arm: Implement SVE gather loads [v2,56/67] target/arm: Implement SVE scatter store vector immediate [v2,57/67] target/arm: Implement SVE floating-point compare vectors [v2,58/67] target/arm: Implement SVE floating-point arithmetic with immediate [v2,59/67] target/arm: Implement SVE Floating Point Multiply Indexed Group [v2,60/67] target/arm: Implement SVE FP Fast Reduction Group [v2,61/67] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group [v2,62/67] target/arm: Implement SVE FP Compare with Zero Group [v2,63/67] target/arm: Implement SVE floating-point trig multiply-add coefficient [v2,64/67] target/arm: Implement SVE floating-point convert precision [v2,65/67] target/arm: Implement SVE floating-point convert to integer [v2,66/67] target/arm: Implement SVE floating-point round to integral value [v2,67/67] target/arm: Implement SVE floating-point unary operations

Message ID

20180217182323.25885-42-richard.henderson@linaro.org

State

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Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Sat, 17 Feb 2018 10:22:57 -0800
Message-Id: <20180217182323.25885-42-richard.henderson@linaro.org>
In-Reply-To: <20180217182323.25885-1-richard.henderson@linaro.org>
References: <20180217182323.25885-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP
Precedence: list
Cc: qemu-arm@nongnu.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Scalable Vector Extension | expand

Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-sve.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 8 ++++++++ 2 files changed, 43 insertions(+) -- 2.14.3

Comments

Peter Maydell Feb. 23, 2018, 5:12 p.m. UTC | #1

On 17 February 2018 at 18:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/translate-sve.c | 35 +++++++++++++++++++++++++++++++++++

>  target/arm/sve.decode      |  8 ++++++++

>  2 files changed, 43 insertions(+)

>


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4b92a55c21..7571d02237 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2939,6 +2939,41 @@  static void trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn)
     tcg_temp_free_i32(t3);
 }
 
+/*
+ *** SVE Integer Wide Immediate - Unpredicated Group
+ */
+
+static void trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
+{
+    unsigned vsz = vec_full_reg_size(s);
+    int dofs = vec_full_reg_offset(s, a->rd);
+    uint64_t imm;
+
+    if (a->esz == 0) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    /* Decode the VFP immediate.  */
+    imm = vfp_expand_imm(a->esz, a->imm);
+    imm = dup_const(a->esz, imm);
+
+    tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
+}
+
+static void trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
+{
+    unsigned vsz = vec_full_reg_size(s);
+    int dofs = vec_full_reg_offset(s, a->rd);
+
+    if (a->esz == 0 && extract32(insn, 13, 1)) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
+}
+
 /*
  *** SVE Memory - 32-bit Gather and Unsized Contiguous Group
  */
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index b5bc7e9546..ea1bfe7579 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -622,6 +622,14 @@  CTERM		00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
 # SVE integer compare scalar count and limit
 WHILE		00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
 
+### SVE Integer Wide Immediate - Unpredicated Group
+
+# SVE broadcast floating-point immediate (unpredicated)
+FDUP		00100101 esz:2 111 00 1110 imm:8 rd:5
+
+# SVE broadcast integer immediate (unpredicated)
+DUP_i		00100101 esz:2 111 00 011 . ........ rd:5	imm=%sh8_i8s
+
 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
 
 # SVE load predicate register

[v2,41/67] target/arm: Implement FDUP/DUP

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