| Message ID | 20180217182323.25885-55-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Scalable Vector Extension | expand |
On 17 February 2018 at 18:23, Richard Henderson <richard.henderson@linaro.org> wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/translate-sve.c | 9 +++++++++ > target/arm/sve.decode | 23 +++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index ca49b94924..63c7a0e8d8 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -3958,3 +3958,12 @@ static void trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn) > do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, > cpu_reg_sp(s, a->rn), fn); > } > + > +/* > + * Prefetches > + */ > + > +static void trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn) > +{ > + /* Prefetch is a nop within QEMU. */ > +} > diff --git a/target/arm/sve.decode b/target/arm/sve.decode > index edd9340c02..f0144aa2d0 100644 > --- a/target/arm/sve.decode > +++ b/target/arm/sve.decode > @@ -801,6 +801,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ > LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ > @rpri_load_msz nreg=0 > > +# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) > +PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- > + > +# SVE 32-bit gather prefetch (vector plus immediate) > +PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- > + > +# SVE contiguous prefetch (scalar plus immediate) > +PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- > + > +# SVE contiguous prefetch (scalar plus scalar) > +PRF 1000010 -- 00 ----- 110 --- ----- 0 ---- This one needs something slightly more complicated, because Rm == 11111 has to be UnallocatedEncoding. I checked the others and they don't have any unallocated cases lurking in their decode pseudocode. thanks -- PMM
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ca49b94924..63c7a0e8d8 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3958,3 +3958,12 @@ static void trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn) do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, cpu_reg_sp(s, a->rn), fn); } + +/* + * Prefetches + */ + +static void trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn) +{ + /* Prefetch is a nop within QEMU. */ +} diff --git a/target/arm/sve.decode b/target/arm/sve.decode index edd9340c02..f0144aa2d0 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -801,6 +801,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ @rpri_load_msz nreg=0 +# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) +PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- + +# SVE 32-bit gather prefetch (vector plus immediate) +PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- + +# SVE contiguous prefetch (scalar plus immediate) +PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- + +# SVE contiguous prefetch (scalar plus scalar) +PRF 1000010 -- 00 ----- 110 --- ----- 0 ---- + +### SVE Memory 64-bit Gather Group + +# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) +PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- + +# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) +PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- + +# SVE 64-bit gather prefetch (vector plus immediate) +PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- + ### SVE Memory Store Group # SVE store predicate register
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-sve.c | 9 +++++++++ target/arm/sve.decode | 23 +++++++++++++++++++++++ 2 files changed, 32 insertions(+) -- 2.14.3