diff mbox series

[1/2] cpu-defs.h: Document CPUIOTLBEntry 'addr' field

Message ID 20180611125633.32755-2-peter.maydell@linaro.org
State Superseded
Headers show
Series cputlb: document iotlb.addr, fix txfail physaddr | expand

Commit Message

Peter Maydell June 11, 2018, 12:56 p.m. UTC 
The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious
use; add a comment documenting it (reverse-engineered from what
the code that sets it is doing).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 include/exec/cpu-defs.h |  9 +++++++++
 accel/tcg/cputlb.c      | 12 ++++++++++++
 2 files changed, 21 insertions(+)

-- 
2.17.1

Comments

Richard Henderson June 12, 2018, 10:09 p.m. UTC | #1 
On 06/11/2018 02:56 AM, Peter Maydell wrote:
> The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious

> use; add a comment documenting it (reverse-engineered from what

> the code that sets it is doing).

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  include/exec/cpu-defs.h |  9 +++++++++

>  accel/tcg/cputlb.c      | 12 ++++++++++++

>  2 files changed, 21 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
Emilio Cota June 13, 2018, 3:33 a.m. UTC | #2 
On Mon, Jun 11, 2018 at 13:56:32 +0100, Peter Maydell wrote:
>  typedef struct CPUIOTLBEntry {

> +    /*

> +     * @addr contains:

> +     *  - in the lower TARGET_PAGE_BITS, a physical section number

> +     *  - with the lower TARGET_PAGE_BITS masked off, an offset which

> +     *    must be added to the virtual address to obtain:

> +     *     + the ramaddr_t of the target RAM (if the physical section


s/ramaddr_t/ram_addr_t/ ? Also in cputlb.c:

> +     * TARGET_PAGE_BITS, and either

> +     *  + the ramaddr_t of the page base of the target RAM (if NOTDIRTY or ROM)


Thanks,

		Emilio
diff mbox series

Patch

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e43ff8346b1..452e82d21c6 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -127,6 +127,15 @@  QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
  * structs into one.)
  */
 typedef struct CPUIOTLBEntry {
+    /*
+     * @addr contains:
+     *  - in the lower TARGET_PAGE_BITS, a physical section number
+     *  - with the lower TARGET_PAGE_BITS masked off, an offset which
+     *    must be added to the virtual address to obtain:
+     *     + the ramaddr_t of the target RAM (if the physical section
+     *       number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
+     *     + the offset within the target MemoryRegion (otherwise)
+     */
     hwaddr addr;
     MemTxAttrs attrs;
 } CPUIOTLBEntry;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 05439039e91..355ded27024 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -664,6 +664,18 @@  void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
 
     /* refill the tlb */
+    /*
+     * At this point iotlb contains a physical section number in the lower
+     * TARGET_PAGE_BITS, and either
+     *  + the ramaddr_t of the page base of the target RAM (if NOTDIRTY or ROM)
+     *  + the offset within section->mr of the page base (otherwise)
+     * We subtract the vaddr (which is page aligned and thus won't
+     * disturb the low bits) to give an offset which can be added to the
+     * (non-page-aligned) vaddr of the eventual memory access to get
+     * the MemoryRegion offset for the access. Note that the vaddr we
+     * subtract here is that of the page base, and not the same as the
+     * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
+     */
     env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
     env->iotlb[mmu_idx][index].attrs = attrs;