| Message ID | 20180612202411.29798-3-nm@ti.com |
|---|---|
| State | Accepted |
| Commit | c2ca3fdfb916dc8baecea88490df20de4244a7e1 |
| Headers | show |
| Series | ARM: Provide workaround setup bits for CVE-2017-5715 (A8/A15) | expand |
On 06/12/2018 10:24 PM, Nishanth Menon wrote: > As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) > needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to > be done unconditionally for Cortex-A15 processors. Provide a config > option for platforms to enable this option based on impact analysis > for products. > > NOTE: This patch in itself is NOT the final solution, this requires: > a) Implementation of v7_arch_cp15_set_acr on SoCs which may not > provide direct access to ACR register. > b) Operating Systems such as Linux to provide adequate workaround in the > right locations. > c) This workaround applies to only the boot processor. It is important > to apply workaround as necessary (context-save-restore) around low > power context loss OR additional processors as necessary in either > firmware support OR elsewhere in OS. > > [1] https://developer.arm.com/support/security-update > [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html > > Cc: Marc Zyngier <marc.zyngier@arm.com> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Tony Lindgren <tony@atomide.com> > Cc: Robin Murphy <robin.murphy@arm.com> > Cc: Florian Fainelli <f.fainelli@gmail.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Christoffer Dall <christoffer.dall@linaro.org> > Cc: Andre Przywara <Andre.Przywara@arm.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Tom Rini <trini@konsulko.com> > Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> > > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > arch/arm/Kconfig | 4 ++++ > arch/arm/cpu/armv7/start.S | 8 ++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 9e32d5b43cb0..98f58fd27696 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -109,6 +109,7 @@ config SYS_ARM_MPU > # CONFIG_ARM_ERRATA_798870 > # CONFIG_ARM_ERRATA_801819 > # CONFIG_ARM_CORTEX_A8_CVE_2017_5715 > +# CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > > config ARM_ERRATA_430973 > bool > @@ -182,6 +183,9 @@ config ARM_ERRATA_855873 > config ARM_CORTEX_A8_CVE_2017_5715 > bool > > +config ARM_CORTEX_A15_CVE_2017_5715 > + bool > + > config CPU_ARM720T > bool > select SYS_CACHE_SHIFT_5 > diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S > index 3beaf5a93d81..81edec01bf32 100644 > --- a/arch/arm/cpu/armv7/start.S > +++ b/arch/arm/cpu/armv7/start.S > @@ -241,6 +241,14 @@ skip_errata_798870: > skip_errata_801819: > #endif > > +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register > + orr r0, r0, #1 << 0 @ Enable invalidates of BTB Can we use BIT() macro in the assembler code too ?
On June 12, 2018 1:24:09 PM PDT, Nishanth Menon <nm@ti.com> wrote: >As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) >needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to >be done unconditionally for Cortex-A15 processors. Provide a config >option for platforms to enable this option based on impact analysis >for products. > >NOTE: This patch in itself is NOT the final solution, this requires: >a) Implementation of v7_arch_cp15_set_acr on SoCs which may not > provide direct access to ACR register. >b) Operating Systems such as Linux to provide adequate workaround in >the > right locations. This is the case as of 4.18 so you could probably reference CONFIG_CPU_SPECTRE and CONFIG_HARDEN_BRANCH_PREDICTOR in a v2. >c) This workaround applies to only the boot processor. It is important > to apply workaround as necessary (context-save-restore) around low > power context loss OR additional processors as necessary in either > firmware support OR elsewhere in OS. About that, I don't know enough of uboot but are there existing PSCI or other seemingly standard secondary core support in uboot that would make us go through the same initialization as the boot CPU? If not, is everything going to be largely implementation specific and scattered between uboot and the hypervisors or kernel? FWIW, this is what prompted me to submit this: https://patchwork.kernel.org/patch/10453643/ > >[1] https://developer.arm.com/support/security-update >[2] >http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html > >Cc: Marc Zyngier <marc.zyngier@arm.com> >Cc: Russell King <linux@arm.linux.org.uk> >Cc: Tony Lindgren <tony@atomide.com> >Cc: Robin Murphy <robin.murphy@arm.com> >Cc: Florian Fainelli <f.fainelli@gmail.com> >Cc: Catalin Marinas <catalin.marinas@arm.com> >Cc: Will Deacon <will.deacon@arm.com> >Cc: Christoffer Dall <christoffer.dall@linaro.org> >Cc: Andre Przywara <Andre.Przywara@arm.com> >Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> >Cc: Tom Rini <trini@konsulko.com> >Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> > >Signed-off-by: Nishanth Menon <nm@ti.com> >--- > arch/arm/Kconfig | 4 ++++ > arch/arm/cpu/armv7/start.S | 8 ++++++++ > 2 files changed, 12 insertions(+) > >diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >index 9e32d5b43cb0..98f58fd27696 100644 >--- a/arch/arm/Kconfig >+++ b/arch/arm/Kconfig >@@ -109,6 +109,7 @@ config SYS_ARM_MPU > # CONFIG_ARM_ERRATA_798870 > # CONFIG_ARM_ERRATA_801819 > # CONFIG_ARM_CORTEX_A8_CVE_2017_5715 >+# CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > > config ARM_ERRATA_430973 > bool >@@ -182,6 +183,9 @@ config ARM_ERRATA_855873 > config ARM_CORTEX_A8_CVE_2017_5715 > bool > >+config ARM_CORTEX_A15_CVE_2017_5715 >+ bool >+ > config CPU_ARM720T > bool > select SYS_CACHE_SHIFT_5 >diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S >index 3beaf5a93d81..81edec01bf32 100644 >--- a/arch/arm/cpu/armv7/start.S >+++ b/arch/arm/cpu/armv7/start.S >@@ -241,6 +241,14 @@ skip_errata_798870: > skip_errata_801819: > #endif > >+#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 >+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register >+ orr r0, r0, #1 << 0 @ Enable invalidates of BTB >+ push {r1-r5} @ Save the cpu info registers >+ bl v7_arch_cp15_set_acr >+ pop {r1-r5} @ Restore the cpu info - fall through >+#endif >+ > #ifdef CONFIG_ARM_ERRATA_454179 > mrc p15, 0, r0, c1, c0, 1 @ Read ACR >
On 23:05-20180612, Marek Vasut wrote: > On 06/12/2018 10:24 PM, Nishanth Menon wrote: [..] > > +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > > + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register > > + orr r0, r0, #1 << 0 @ Enable invalidates of BTB > > Can we use BIT() macro in the assembler code too ? Probably, but just following convention in the rest of the file. Do we want to change from existing code?
On 00:30-20180613, Florian Fainelli wrote: > On June 12, 2018 1:24:09 PM PDT, Nishanth Menon <nm@ti.com> wrote: > >As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) > >needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to > >be done unconditionally for Cortex-A15 processors. Provide a config > >option for platforms to enable this option based on impact analysis > >for products. > > > >NOTE: This patch in itself is NOT the final solution, this requires: > >a) Implementation of v7_arch_cp15_set_acr on SoCs which may not > > provide direct access to ACR register. > >b) Operating Systems such as Linux to provide adequate workaround in > >the > > right locations. > > This is the case as of 4.18 so you could probably reference CONFIG_CPU_SPECTRE and CONFIG_HARDEN_BRANCH_PREDICTOR in a v2. Did'nt want to tie the description too deep to Linux specifics.. Linux documents itself and users are encouraged to read that documentation, correct? > > >c) This workaround applies to only the boot processor. It is important > > to apply workaround as necessary (context-save-restore) around low > > power context loss OR additional processors as necessary in either > > firmware support OR elsewhere in OS. > > About that, I don't know enough of uboot but are there existing PSCI or > other seemingly standard secondary core support in uboot that would make > us go through the same initialization as the boot CPU? If not, is > everything going to be largely implementation specific and > scattered between uboot and the hypervisors or kernel? in ARMV7 SoCs, unfortunately, we lived in a world of no-exact-standard. even within TI, Few of the SoCs use PSCI, others did implement custom SMC calls (since they existed in an architecture prior to PSCI). > > FWIW, this is what prompted me to submit this: > > https://patchwork.kernel.org/patch/10453643/ That wont work in a generic manner for precisely the same reason I had to do it with weak function in u-boot (some SoCs will only permit 'mcr p15, 0, r0, c1, c0, 1' in secure world and you need to make a custom smc call to make it happen). Unfortunately, IMHO, at least at this point, there'd be custom implementations per SoC and layers depending on where to implement it.
On Wed, Jun 13, 2018 at 08:32:15AM -0500, Nishanth Menon wrote: > On 23:05-20180612, Marek Vasut wrote: > > On 06/12/2018 10:24 PM, Nishanth Menon wrote: > [..] > > > +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > > > + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register > > > + orr r0, r0, #1 << 0 @ Enable invalidates of BTB > > > > Can we use BIT() macro in the assembler code too ? > > Probably, but just following convention in the rest of the file. Do we > want to change from existing code? Agreed, we should follow the existing style (and I'm not 100% sure I like using BIT() in asm files). -- Tom
On 15:46-20180613, Tom Rini wrote: > On Wed, Jun 13, 2018 at 08:32:15AM -0500, Nishanth Menon wrote: > > On 23:05-20180612, Marek Vasut wrote: > > > On 06/12/2018 10:24 PM, Nishanth Menon wrote: > > [..] > > > > +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 > > > > + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register > > > > + orr r0, r0, #1 << 0 @ Enable invalidates of BTB > > > > > > Can we use BIT() macro in the assembler code too ? > > > > Probably, but just following convention in the rest of the file. Do we > > want to change from existing code? > > Agreed, we should follow the existing style (and I'm not 100% sure I > like using BIT() in asm files). OK. Will drop this feedback about BIT() macro if I have to do a v2.
On 06/13/2018 06:37 AM, Nishanth Menon wrote: > On 00:30-20180613, Florian Fainelli wrote: >> On June 12, 2018 1:24:09 PM PDT, Nishanth Menon <nm@ti.com> wrote: >>> As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) >>> needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to >>> be done unconditionally for Cortex-A15 processors. Provide a config >>> option for platforms to enable this option based on impact analysis >>> for products. >>> >>> NOTE: This patch in itself is NOT the final solution, this requires: >>> a) Implementation of v7_arch_cp15_set_acr on SoCs which may not >>> provide direct access to ACR register. >>> b) Operating Systems such as Linux to provide adequate workaround in >>> the >>> right locations. >> >> This is the case as of 4.18 so you could probably reference CONFIG_CPU_SPECTRE and CONFIG_HARDEN_BRANCH_PREDICTOR in a v2. > > Did'nt want to tie the description too deep to Linux specifics.. Linux > documents itself and users are encouraged to read that documentation, > correct? That's fair enough I guess, we also don't know how the other OSes do provide that mitigation and whether they have run-time/build-time configuration options gating those. > >> >>> c) This workaround applies to only the boot processor. It is important >>> to apply workaround as necessary (context-save-restore) around low >>> power context loss OR additional processors as necessary in either >>> firmware support OR elsewhere in OS. >> >> About that, I don't know enough of uboot but are there existing PSCI or >> other seemingly standard secondary core support in uboot that would make >> us go through the same initialization as the boot CPU? If not, is >> everything going to be largely implementation specific and >> scattered between uboot and the hypervisors or kernel? > > in ARMV7 SoCs, unfortunately, we lived in a world of no-exact-standard. > even within TI, Few of the SoCs use PSCI, others did implement custom > SMC calls (since they existed in an architecture prior to PSCI). > >> >> FWIW, this is what prompted me to submit this: >> >> https://patchwork.kernel.org/patch/10453643/ > > That wont work in a generic manner for precisely the same reason I had to do > it with weak function in u-boot (some SoCs will only permit 'mcr > p15, 0, r0, c1, c0, 1' in secure world and you need to make a custom smc > call to make it happen). Unfortunately, IMHO, at least at this > point, there'd be custom implementations per SoC and layers depending on > where to implement it. It won't work in a generic manner but it will work for some platforms where updating the firmware is impractical, and since the bits are write ignore if your PL does not allow it, this still seems like a net win for platforms where this is effective, and it does take care of Linux doing the SMP bring-up of secondary cores as well. That's what we have in our downstream tree at least, and I was hoping this could land upstream too.
On 06/13/2018 11:32 PM, Nishanth Menon wrote: > On 15:46-20180613, Tom Rini wrote: >> On Wed, Jun 13, 2018 at 08:32:15AM -0500, Nishanth Menon wrote: >>> On 23:05-20180612, Marek Vasut wrote: >>>> On 06/12/2018 10:24 PM, Nishanth Menon wrote: >>> [..] >>>>> +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 >>>>> + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register >>>>> + orr r0, r0, #1 << 0 @ Enable invalidates of BTB >>>> >>>> Can we use BIT() macro in the assembler code too ? >>> >>> Probably, but just following convention in the rest of the file. Do we >>> want to change from existing code? >> >> Agreed, we should follow the existing style (and I'm not 100% sure I >> like using BIT() in asm files). > > OK. Will drop this feedback about BIT() macro if I have to do a v2. Fine by me
On 21:36-20180613, Florian Fainelli wrote: [...] > >>> c) This workaround applies to only the boot processor. It is important > >>> to apply workaround as necessary (context-save-restore) around low > >>> power context loss OR additional processors as necessary in either > >>> firmware support OR elsewhere in OS. > >> > >> About that, I don't know enough of uboot but are there existing PSCI or > >> other seemingly standard secondary core support in uboot that would make > >> us go through the same initialization as the boot CPU? If not, is > >> everything going to be largely implementation specific and > >> scattered between uboot and the hypervisors or kernel? > > > > in ARMV7 SoCs, unfortunately, we lived in a world of no-exact-standard. > > even within TI, Few of the SoCs use PSCI, others did implement custom > > SMC calls (since they existed in an architecture prior to PSCI). > > > >> > >> FWIW, this is what prompted me to submit this: > >> > >> https://patchwork.kernel.org/patch/10453643/ > > > > That wont work in a generic manner for precisely the same reason I had to do > > it with weak function in u-boot (some SoCs will only permit 'mcr > > p15, 0, r0, c1, c0, 1' in secure world and you need to make a custom smc > > call to make it happen). Unfortunately, IMHO, at least at this > > point, there'd be custom implementations per SoC and layers depending on > > where to implement it. > > It won't work in a generic manner but it will work for some platforms > where updating the firmware is impractical, and since the bits are write > ignore if your PL does not allow it, this still seems like a net win for > platforms where this is effective, and it does take care of Linux doing > the SMP bring-up of secondary cores as well. That's what we have in our > downstream tree at least, and I was hoping this could land upstream too. I think it is clear from Russell's summary that we dont want "may work" workaround in kernel/bootloaders. in case of u-boot (which this patch is about), I'd suggest adding the CONFIG_*CVE* input to the Kconfig for the SoC where you know for sure this works. Does that sound a fair tradeoff?
On Tue, Jun 12, 2018 at 5:24 PM, Nishanth Menon <nm@ti.com> wrote: > As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) > needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to > be done unconditionally for Cortex-A15 processors. Provide a config > option for platforms to enable this option based on impact analysis > for products. > > NOTE: This patch in itself is NOT the final solution, this requires: > a) Implementation of v7_arch_cp15_set_acr on SoCs which may not > provide direct access to ACR register. > b) Operating Systems such as Linux to provide adequate workaround in the > right locations. > c) This workaround applies to only the boot processor. It is important > to apply workaround as necessary (context-save-restore) around low > power context loss OR additional processors as necessary in either > firmware support OR elsewhere in OS. > > [1] https://developer.arm.com/support/security-update > [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html > > Cc: Marc Zyngier <marc.zyngier@arm.com> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Tony Lindgren <tony@atomide.com> > Cc: Robin Murphy <robin.murphy@arm.com> > Cc: Florian Fainelli <f.fainelli@gmail.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Christoffer Dall <christoffer.dall@linaro.org> > Cc: Andre Przywara <Andre.Przywara@arm.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Tom Rini <trini@konsulko.com> > Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> > > Signed-off-by: Nishanth Menon <nm@ti.com> On a imx51-babbage board: Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
On Tue, Jun 12, 2018 at 03:24:09PM -0500, Nishanth Menon wrote: > As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) > needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to > be done unconditionally for Cortex-A15 processors. Provide a config > option for platforms to enable this option based on impact analysis > for products. > > NOTE: This patch in itself is NOT the final solution, this requires: > a) Implementation of v7_arch_cp15_set_acr on SoCs which may not > provide direct access to ACR register. > b) Operating Systems such as Linux to provide adequate workaround in the > right locations. > c) This workaround applies to only the boot processor. It is important > to apply workaround as necessary (context-save-restore) around low > power context loss OR additional processors as necessary in either > firmware support OR elsewhere in OS. > > [1] https://developer.arm.com/support/security-update > [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html > > Cc: Marc Zyngier <marc.zyngier@arm.com> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Tony Lindgren <tony@atomide.com> > Cc: Robin Murphy <robin.murphy@arm.com> > Cc: Florian Fainelli <f.fainelli@gmail.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Christoffer Dall <christoffer.dall@linaro.org> > Cc: Andre Przywara <Andre.Przywara@arm.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Tom Rini <trini@konsulko.com> > Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> > > Signed-off-by: Nishanth Menon <nm@ti.com> > Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Applied to u-boot/master, thanks! -- Tom
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9e32d5b43cb0..98f58fd27696 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -109,6 +109,7 @@ config SYS_ARM_MPU # CONFIG_ARM_ERRATA_798870 # CONFIG_ARM_ERRATA_801819 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715 +# CONFIG_ARM_CORTEX_A15_CVE_2017_5715 config ARM_ERRATA_430973 bool @@ -182,6 +183,9 @@ config ARM_ERRATA_855873 config ARM_CORTEX_A8_CVE_2017_5715 bool +config ARM_CORTEX_A15_CVE_2017_5715 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 3beaf5a93d81..81edec01bf32 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -241,6 +241,14 @@ skip_errata_798870: skip_errata_801819: #endif +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 0 @ Enable invalidates of BTB + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through +#endif + #ifdef CONFIG_ARM_ERRATA_454179 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: Nishanth Menon <nm@ti.com> --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/start.S | 8 ++++++++ 2 files changed, 12 insertions(+)