| Message ID | 1532684275-13041-3-git-send-email-Richard.Earnshaw@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | (v2) Mitigation against unsafe data speculation (CVE-2017-5753) | expand |
On Fri, 27 Jul 2018 at 11:38, Richard Earnshaw <Richard.Earnshaw@arm.com> wrote: > > > This patch defines a speculation barrier for AArch32. > > * config/arm/unspecs.md (unspecv): Add VUNSPEC_SPECULATION_BARRIER. > * config/arm/arm.md (speculation_barrier): New expand. > (speculation_barrier_insn): New pattern. > --- Hi Richard, This patch causes compilation errors for c-c++-common/spec-barrier-2.c when compiled for old architectures (eg -march=armv5t): /ccrf2LoR.s:49: Error: selected processor does not support `isb' in ARM mode /ccrf2LoR.s:50: Error: selected processor does not support `dsb sy' in ARM mode Does this belong to the kind of failures you still expect from this patch series?
On 06/08/18 15:00, Christophe Lyon wrote: > On Fri, 27 Jul 2018 at 11:38, Richard Earnshaw <Richard.Earnshaw@arm.com> wrote: >> >> >> This patch defines a speculation barrier for AArch32. >> >> * config/arm/unspecs.md (unspecv): Add VUNSPEC_SPECULATION_BARRIER. >> * config/arm/arm.md (speculation_barrier): New expand. >> (speculation_barrier_insn): New pattern. >> --- > > Hi Richard, > > This patch causes compilation errors for c-c++-common/spec-barrier-2.c > when compiled for old architectures (eg -march=armv5t): > /ccrf2LoR.s:49: Error: selected processor does not support `isb' in ARM mode > /ccrf2LoR.s:50: Error: selected processor does not support `dsb sy' in ARM mode > > Does this belong to the kind of failures you still expect from this > patch series? > Nope :-( I'll look into it. We may need to just disable these patterns for architectures that old. Thumb1 code on pre-v6t2 similarly can't be protected. Thanks for reporting. R.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 361a026..ca2a2f5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12012,6 +12012,27 @@ (define_insn "<mrrc>" [(set_attr "length" "4") (set_attr "type" "coproc")]) +(define_expand "speculation_barrier" + [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)] + "TARGET_EITHER" + " + /* Don't emit anything for Thumb1 and suppress the warning from the + generic expansion. */ + if (!TARGET_32BIT) + DONE; + " +) + +;; Generate a hard speculation barrier when we have not enabled speculation +;; tracking. +(define_insn "*speculation_barrier_insn" + [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)] + "TARGET_32BIT" + "isb\;dsb\\tsy" + [(set_attr "type" "block") + (set_attr "length" "8")] +) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index b05f85e..1941673 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -168,6 +168,7 @@ (define_c_enum "unspecv" [ VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction. VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction. VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction. + VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier. ]) ;; Enumerators for NEON unspecs.