diff mbox series

[v4,08/40] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*

Message ID 20191203022937.1474-9-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Implement ARMv8.1-VHE | expand

Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m. UTC 
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h           |  8 ++++----
 target/arm/internals.h     |  4 ++--
 target/arm/helper.c        | 40 +++++++++++++++++++-------------------
 target/arm/translate-a64.c |  4 ++--
 target/arm/translate.c     |  6 +++---
 5 files changed, 31 insertions(+), 31 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Dec. 4, 2019, 10:38 a.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:

> This is part of a reorganization to the set of mmu_idx.

> This emphasizes that they apply to the EL1&0 regime.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/cpu.h           |  8 ++++----

>  target/arm/internals.h     |  4 ++--

>  target/arm/helper.c        | 40 +++++++++++++++++++-------------------

>  target/arm/translate-a64.c |  4 ++--

>  target/arm/translate.c     |  6 +++---

>  5 files changed, 31 insertions(+), 31 deletions(-)

>

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index 9729e62d2c..802cddd2df 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -2864,8 +2864,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,

>  #define ARM_MMU_IDX_COREIDX_MASK 0x7

>  

>  typedef enum ARMMMUIdx {

> -    ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,

> -    ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,

> +    ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,

> +    ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,

>      ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,

>      ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,

>      ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,

> @@ -2890,8 +2890,8 @@ typedef enum ARMMMUIdx {

>   * for use when calling tlb_flush_by_mmuidx() and friends.

>   */

>  typedef enum ARMMMUIdxBit {

> -    ARMMMUIdxBit_S12NSE0 = 1 << 0,

> -    ARMMMUIdxBit_S12NSE1 = 1 << 1,

> +    ARMMMUIdxBit_EL10_0 = 1 << 0,

> +    ARMMMUIdxBit_EL10_1 = 1 << 1,

>      ARMMMUIdxBit_S1E2 = 1 << 2,

>      ARMMMUIdxBit_S1E3 = 1 << 3,

>      ARMMMUIdxBit_S1SE0 = 1 << 4,

> diff --git a/target/arm/internals.h b/target/arm/internals.h

> index f5313dd3d4..54142dd789 100644

> --- a/target/arm/internals.h

> +++ b/target/arm/internals.h

> @@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)

>  static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)

>  {

>      switch (mmu_idx) {

> -    case ARMMMUIdx_S12NSE0:

> -    case ARMMMUIdx_S12NSE1:

> +    case ARMMMUIdx_EL10_0:

> +    case ARMMMUIdx_EL10_1:

>      case ARMMMUIdx_S1NSE0:

>      case ARMMMUIdx_S1NSE1:

>      case ARMMMUIdx_S1E2:

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 6c09cda4ea..d2b90763ca 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -670,8 +670,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,

>      CPUState *cs = env_cpu(env);

>  

>      tlb_flush_by_mmuidx(cs,

> -                        ARMMMUIdxBit_S12NSE1 |

> -                        ARMMMUIdxBit_S12NSE0 |

> +                        ARMMMUIdxBit_EL10_1 |

> +                        ARMMMUIdxBit_EL10_0 |

>                          ARMMMUIdxBit_S2NS);

>  }

>  

> @@ -681,8 +681,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

>      CPUState *cs = env_cpu(env);

>  

>      tlb_flush_by_mmuidx_all_cpus_synced(cs,

> -                                        ARMMMUIdxBit_S12NSE1 |

> -                                        ARMMMUIdxBit_S12NSE0 |

> +                                        ARMMMUIdxBit_EL10_1 |

> +                                        ARMMMUIdxBit_EL10_0 |

>                                          ARMMMUIdxBit_S2NS);

>  }

>  

> @@ -3068,7 +3068,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

>          format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);

>  

>          if (arm_feature(env, ARM_FEATURE_EL2)) {

> -            if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {

> +            if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {

>                  format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);

>              } else {

>                  format64 |= arm_current_el(env) == 2;

> @@ -3167,11 +3167,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>          break;

>      case 4:

>          /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */

> -        mmu_idx = ARMMMUIdx_S12NSE1;

> +        mmu_idx = ARMMMUIdx_EL10_1;

>          break;

>      case 6:

>          /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */

> -        mmu_idx = ARMMMUIdx_S12NSE0;

> +        mmu_idx = ARMMMUIdx_EL10_0;

>          break;

>      default:

>          g_assert_not_reached();

> @@ -3229,10 +3229,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,

>          mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;

>          break;

>      case 4: /* AT S12E1R, AT S12E1W */

> -        mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;

> +        mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1;

>          break;

>      case 6: /* AT S12E0R, AT S12E0W */

> -        mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;

> +        mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0;

>          break;

>      default:

>          g_assert_not_reached();

> @@ -3531,8 +3531,8 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

>      /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */

>      if (raw_read(env, ri) != value) {

>          tlb_flush_by_mmuidx(cs,

> -                            ARMMMUIdxBit_S12NSE1 |

> -                            ARMMMUIdxBit_S12NSE0 |

> +                            ARMMMUIdxBit_EL10_1 |

> +                            ARMMMUIdxBit_EL10_0 |

>                              ARMMMUIdxBit_S2NS);

>          raw_write(env, ri, value);

>      }

> @@ -3893,7 +3893,7 @@ static int vae1_tlbmask(CPUARMState *env)

>      if (arm_is_secure_below_el3(env)) {

>          return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;

>      } else {

> -        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;

> +        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;

>      }

>  }

>  

> @@ -3929,9 +3929,9 @@ static int vmalle1_tlbmask(CPUARMState *env)

>      if (arm_is_secure_below_el3(env)) {

>          return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;

>      } else if (arm_feature(env, ARM_FEATURE_EL2)) {

> -        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;

> +        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS;

>      } else {

> -        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;

> +        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;

>      }

>  }

>  

> @@ -8671,8 +8671,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)

>   */

>  static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)

>  {

> -    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {

> -        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);

> +    if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {

> +        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0);

>      }

>      return mmu_idx;

>  }

> @@ -8715,8 +8715,8 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)

>          return true;

>      default:

>          return false;

> -    case ARMMMUIdx_S12NSE0:

> -    case ARMMMUIdx_S12NSE1:

> +    case ARMMMUIdx_EL10_0:

> +    case ARMMMUIdx_EL10_1:

>          g_assert_not_reached();

>      }

>  }

> @@ -10620,7 +10620,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

>                     target_ulong *page_size,

>                     ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)

>  {

> -    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {

> +    if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {

>          /* Call ourselves recursively to do the stage 1 and then stage 2

>           * translations.

>           */

> @@ -11148,7 +11148,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)

>      if (el < 2 && arm_is_secure_below_el3(env)) {

>          return ARMMMUIdx_S1SE0 + el;

>      } else {

> -        return ARMMMUIdx_S12NSE0 + el;

> +        return ARMMMUIdx_EL10_0 + el;

>      }

>  }

>  

> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

> index d4bebbe629..2703ebf32a 100644

> --- a/target/arm/translate-a64.c

> +++ b/target/arm/translate-a64.c

> @@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)

>      ARMMMUIdx useridx;

>  

>      switch (s->mmu_idx) {

> -    case ARMMMUIdx_S12NSE1:

> -        useridx = ARMMMUIdx_S12NSE0;

> +    case ARMMMUIdx_EL10_1:

> +        useridx = ARMMMUIdx_EL10_0;

>          break;

>      case ARMMMUIdx_S1SE1:

>          useridx = ARMMMUIdx_S1SE0;

> diff --git a/target/arm/translate.c b/target/arm/translate.c

> index 4d5d4bd888..e3deea50e0 100644

> --- a/target/arm/translate.c

> +++ b/target/arm/translate.c

> @@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)

>       */

>      switch (s->mmu_idx) {

>      case ARMMMUIdx_S1E2:        /* this one is UNPREDICTABLE */

> -    case ARMMMUIdx_S12NSE0:

> -    case ARMMMUIdx_S12NSE1:

> -        return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);

> +    case ARMMMUIdx_EL10_0:

> +    case ARMMMUIdx_EL10_1:

> +        return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);

>      case ARMMMUIdx_S1E3:

>      case ARMMMUIdx_S1SE0:

>      case ARMMMUIdx_S1SE1:



-- 
Alex Bennée
Peter Maydell Dec. 6, 2019, 3:45 p.m. UTC | #2 
On Tue, 3 Dec 2019 at 02:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> This is part of a reorganization to the set of mmu_idx.

> This emphasizes that they apply to the EL1&0 regime.


It loses the important point that they are stage 1&2
translations rather than stage 1 or stage 2, though,
and also now they're out of line with the naming convention
that all the other indexes use :-(

thanks
-- PMM
Richard Henderson Dec. 6, 2019, 6 p.m. UTC | #3 
On 12/6/19 7:45 AM, Peter Maydell wrote:
> On Tue, 3 Dec 2019 at 02:29, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> This is part of a reorganization to the set of mmu_idx.

>> This emphasizes that they apply to the EL1&0 regime.

> 

> It loses the important point that they are stage 1&2

> translations rather than stage 1 or stage 2, though,

> and also now they're out of line with the naming convention

> that all the other indexes use :-(


It won't be out of line once all of the other renamings are done.


r~
Peter Maydell Dec. 6, 2019, 6:01 p.m. UTC | #4 
On Fri, 6 Dec 2019 at 18:00, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 12/6/19 7:45 AM, Peter Maydell wrote:

> > On Tue, 3 Dec 2019 at 02:29, Richard Henderson

> > <richard.henderson@linaro.org> wrote:

> >>

> >> This is part of a reorganization to the set of mmu_idx.

> >> This emphasizes that they apply to the EL1&0 regime.

> >

> > It loses the important point that they are stage 1&2

> > translations rather than stage 1 or stage 2, though,

> > and also now they're out of line with the naming convention

> > that all the other indexes use :-(

>

> It won't be out of line once all of the other renamings are done.


I think it might be easier to review if I could see
the intended final set of names in one place (eg in
the commit message to this patch), rather than getting
them a bit at a time (though that is definitely the right
way to structure the code changes themselves).

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9729e62d2c..802cddd2df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2864,8 +2864,8 @@  static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
 #define ARM_MMU_IDX_COREIDX_MASK 0x7
 
 typedef enum ARMMMUIdx {
-    ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
-    ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
+    ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
+    ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
     ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
     ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
     ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
@@ -2890,8 +2890,8 @@  typedef enum ARMMMUIdx {
  * for use when calling tlb_flush_by_mmuidx() and friends.
  */
 typedef enum ARMMMUIdxBit {
-    ARMMMUIdxBit_S12NSE0 = 1 << 0,
-    ARMMMUIdxBit_S12NSE1 = 1 << 1,
+    ARMMMUIdxBit_EL10_0 = 1 << 0,
+    ARMMMUIdxBit_EL10_1 = 1 << 1,
     ARMMMUIdxBit_S1E2 = 1 << 2,
     ARMMMUIdxBit_S1E3 = 1 << 3,
     ARMMMUIdxBit_S1SE0 = 1 << 4,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f5313dd3d4..54142dd789 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -808,8 +808,8 @@  static inline void arm_call_el_change_hook(ARMCPU *cpu)
 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
-    case ARMMMUIdx_S12NSE0:
-    case ARMMMUIdx_S12NSE1:
+    case ARMMMUIdx_EL10_0:
+    case ARMMMUIdx_EL10_1:
     case ARMMMUIdx_S1NSE0:
     case ARMMMUIdx_S1NSE1:
     case ARMMMUIdx_S1E2:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6c09cda4ea..d2b90763ca 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -670,8 +670,8 @@  static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = env_cpu(env);
 
     tlb_flush_by_mmuidx(cs,
-                        ARMMMUIdxBit_S12NSE1 |
-                        ARMMMUIdxBit_S12NSE0 |
+                        ARMMMUIdxBit_EL10_1 |
+                        ARMMMUIdxBit_EL10_0 |
                         ARMMMUIdxBit_S2NS);
 }
 
@@ -681,8 +681,8 @@  static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = env_cpu(env);
 
     tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                        ARMMMUIdxBit_S12NSE1 |
-                                        ARMMMUIdxBit_S12NSE0 |
+                                        ARMMMUIdxBit_EL10_1 |
+                                        ARMMMUIdxBit_EL10_0 |
                                         ARMMMUIdxBit_S2NS);
 }
 
@@ -3068,7 +3068,7 @@  static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
         format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
 
         if (arm_feature(env, ARM_FEATURE_EL2)) {
-            if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+            if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
                 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
             } else {
                 format64 |= arm_current_el(env) == 2;
@@ -3167,11 +3167,11 @@  static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         break;
     case 4:
         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
-        mmu_idx = ARMMMUIdx_S12NSE1;
+        mmu_idx = ARMMMUIdx_EL10_1;
         break;
     case 6:
         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
-        mmu_idx = ARMMMUIdx_S12NSE0;
+        mmu_idx = ARMMMUIdx_EL10_0;
         break;
     default:
         g_assert_not_reached();
@@ -3229,10 +3229,10 @@  static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
         break;
     case 4: /* AT S12E1R, AT S12E1W */
-        mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
+        mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1;
         break;
     case 6: /* AT S12E0R, AT S12E0W */
-        mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
+        mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0;
         break;
     default:
         g_assert_not_reached();
@@ -3531,8 +3531,8 @@  static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
     if (raw_read(env, ri) != value) {
         tlb_flush_by_mmuidx(cs,
-                            ARMMMUIdxBit_S12NSE1 |
-                            ARMMMUIdxBit_S12NSE0 |
+                            ARMMMUIdxBit_EL10_1 |
+                            ARMMMUIdxBit_EL10_0 |
                             ARMMMUIdxBit_S2NS);
         raw_write(env, ri, value);
     }
@@ -3893,7 +3893,7 @@  static int vae1_tlbmask(CPUARMState *env)
     if (arm_is_secure_below_el3(env)) {
         return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
     } else {
-        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
     }
 }
 
@@ -3929,9 +3929,9 @@  static int vmalle1_tlbmask(CPUARMState *env)
     if (arm_is_secure_below_el3(env)) {
         return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
     } else if (arm_feature(env, ARM_FEATURE_EL2)) {
-        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
+        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS;
     } else {
-        return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+        return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
     }
 }
 
@@ -8671,8 +8671,8 @@  static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
  */
 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
 {
-    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
-        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
+    if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
+        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0);
     }
     return mmu_idx;
 }
@@ -8715,8 +8715,8 @@  static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
         return true;
     default:
         return false;
-    case ARMMMUIdx_S12NSE0:
-    case ARMMMUIdx_S12NSE1:
+    case ARMMMUIdx_EL10_0:
+    case ARMMMUIdx_EL10_1:
         g_assert_not_reached();
     }
 }
@@ -10620,7 +10620,7 @@  bool get_phys_addr(CPUARMState *env, target_ulong address,
                    target_ulong *page_size,
                    ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
 {
-    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+    if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
         /* Call ourselves recursively to do the stage 1 and then stage 2
          * translations.
          */
@@ -11148,7 +11148,7 @@  ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
     if (el < 2 && arm_is_secure_below_el3(env)) {
         return ARMMMUIdx_S1SE0 + el;
     } else {
-        return ARMMMUIdx_S12NSE0 + el;
+        return ARMMMUIdx_EL10_0 + el;
     }
 }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d4bebbe629..2703ebf32a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -113,8 +113,8 @@  static inline int get_a64_user_mem_index(DisasContext *s)
     ARMMMUIdx useridx;
 
     switch (s->mmu_idx) {
-    case ARMMMUIdx_S12NSE1:
-        useridx = ARMMMUIdx_S12NSE0;
+    case ARMMMUIdx_EL10_1:
+        useridx = ARMMMUIdx_EL10_0;
         break;
     case ARMMMUIdx_S1SE1:
         useridx = ARMMMUIdx_S1SE0;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4d5d4bd888..e3deea50e0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -153,9 +153,9 @@  static inline int get_a32_user_mem_index(DisasContext *s)
      */
     switch (s->mmu_idx) {
     case ARMMMUIdx_S1E2:        /* this one is UNPREDICTABLE */
-    case ARMMMUIdx_S12NSE0:
-    case ARMMMUIdx_S12NSE1:
-        return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
+    case ARMMMUIdx_EL10_0:
+    case ARMMMUIdx_EL10_1:
+        return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
     case ARMMMUIdx_S1E3:
     case ARMMMUIdx_S1SE0:
     case ARMMMUIdx_S1SE1: