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[v2,00/12] mips: Add initial Octeon MIPS64 base support

Message ID 20200514095912.14428-1-sr@denx.de
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Series mips: Add initial Octeon MIPS64 base support | expand

Message

Stefan Roese May 14, 2020, 9:59 a.m. UTC 
This patch adds very basic support for the Octeon III SoCs. Only CFI
parallel UART, reset and NOR flash are supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches later.
To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III
CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such
boards.

Thanks,
Stefan

Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom lowlevel
  init code is currently added in the custom lowlevel_init.S. This needs
  to be extended with necessary code, like errata handling etc. But for
  a very first basic port, this seems to be all thats needed to boot on
  the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
  for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
  to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ

Aaron Williams (2):
  mips: mipsregs.h: Add more register macros for Octeon port
  mips: octeon: Initial minimal support for the Marvell Octeon SoC

Stefan Roese (10):
  mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET
  mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON
  mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
  mips: cache: Make flush_cache() weak to enable overwrite
  mips: time: Only compile the weak get_tbclk() when needed
  mips: traps: Set WG bit in EBase register on Octeon
  mips: mipsregs.h: Sync with linux v5.7.0-rc3 version
  sysreset: Add Octeon sysreset driver
  mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
  mips: octeon: Add minimal Octeon 3 EBB7304 EVK support

 MAINTAINERS                                   |  7 ++
 arch/mips/Kconfig                             | 43 +++++++++
 arch/mips/Makefile                            |  3 +
 arch/mips/cpu/start.S                         |  6 ++
 arch/mips/cpu/time.c                          |  2 +
 arch/mips/dts/Makefile                        |  1 +
 arch/mips/dts/mrvl,cn73xx.dtsi                | 64 +++++++++++++
 arch/mips/dts/mrvl,octeon-ebb7304.dts         | 96 +++++++++++++++++++
 arch/mips/include/asm/cm.h                    | 12 +++
 arch/mips/include/asm/mipsregs.h              | 64 +++++++++----
 arch/mips/lib/cache.c                         |  4 +-
 arch/mips/lib/traps.c                         |  4 +
 arch/mips/mach-octeon/Kconfig                 | 67 +++++++++++++
 arch/mips/mach-octeon/Makefile                | 10 ++
 arch/mips/mach-octeon/cache.c                 | 20 ++++
 arch/mips/mach-octeon/clock.c                 | 27 ++++++
 arch/mips/mach-octeon/cpu.c                   | 55 +++++++++++
 arch/mips/mach-octeon/dram.c                  | 27 ++++++
 arch/mips/mach-octeon/include/ioremap.h       | 30 ++++++
 arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++
 arch/mips/mach-octeon/include/mach/clock.h    | 24 +++++
 arch/mips/mach-octeon/lowlevel_init.S         | 75 +++++++++++++++
 board/Marvell/octeon_ebb7304/Kconfig          | 19 ++++
 board/Marvell/octeon_ebb7304/MAINTAINERS      |  7 ++
 board/Marvell/octeon_ebb7304/Makefile         |  8 ++
 board/Marvell/octeon_ebb7304/board.c          | 12 +++
 configs/octeon_ebb7304_defconfig              | 34 +++++++
 drivers/sysreset/Kconfig                      |  7 ++
 drivers/sysreset/Makefile                     |  1 +
 drivers/sysreset/sysreset_octeon.c            | 52 ++++++++++
 include/configs/octeon_common.h               | 25 +++++
 include/configs/octeon_ebb7304.h              | 20 ++++
 scripts/config_whitelist.txt                  |  1 -
 33 files changed, 846 insertions(+), 23 deletions(-)
 create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi
 create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
 create mode 100644 arch/mips/mach-octeon/Kconfig
 create mode 100644 arch/mips/mach-octeon/Makefile
 create mode 100644 arch/mips/mach-octeon/cache.c
 create mode 100644 arch/mips/mach-octeon/clock.c
 create mode 100644 arch/mips/mach-octeon/cpu.c
 create mode 100644 arch/mips/mach-octeon/dram.c
 create mode 100644 arch/mips/mach-octeon/include/ioremap.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h
 create mode 100644 arch/mips/mach-octeon/include/mach/clock.h
 create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
 create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
 create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
 create mode 100644 board/Marvell/octeon_ebb7304/Makefile
 create mode 100644 board/Marvell/octeon_ebb7304/board.c
 create mode 100644 configs/octeon_ebb7304_defconfig
 create mode 100644 drivers/sysreset/sysreset_octeon.c
 create mode 100644 include/configs/octeon_common.h
 create mode 100644 include/configs/octeon_ebb7304.h

Comments

Stefan Roese May 26, 2020, 12:23 p.m. UTC | #1 
Hi Daniel,

On 14.05.20 11:59, Stefan Roese wrote:
> 
> This patch adds very basic support for the Octeon III SoCs. Only CFI
> parallel UART, reset and NOR flash are supported for now.
> 
> Please note that the basic Octeon port does not include the DDR3/4
> initialization yet. This will be added in some follow-up patches later.
> To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III
> CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such
> boards.
> 
> Thanks,
> Stefan
> 
> Changes in v2:
> - New patch
> - New patch
> - Restructure patch by adding empty functions to asm/cm.h instead
> - New patch
> - New patch
> - Move bit macro definition to mipsregs.h
> - Remove custom start.S and use common start.S. Minimal custom lowlevel
>    init code is currently added in the custom lowlevel_init.S. This needs
>    to be extended with necessary code, like errata handling etc. But for
>    a very first basic port, this seems to be all thats needed to boot on
>    the EBB7304 to the prompt.
> - Removed select CREATE_ARCH_SYMLINK
> - Removed Octeon II support, as its currently no added in this patchset
> - Added cache.c to add the platform specific cache functions as no-ops
>    for Octeon as the platform is cache coherent
> - Removed CONFIG_MIPS_CACHE_COHERENT
> - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
>    to enable better sync with the Linux files in the future
> - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
> - Removed CONFIG_SYS_MIPS_TIMER_FREQ

Daniel, do you have any comments and / or change requests to v2 of this
base Octeon patchset?

Thanks,
Stefan