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[0/5] Support RISC-V migration

Message ID 20200929020337.1559-1-jiangyifei@huawei.com
Headers show
Series Support RISC-V migration | expand

Message

Jiangyifei Sept. 29, 2020, 2:03 a.m. UTC 
This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.

A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.

Yifei Jiang (5):
  target/riscv: Add basic vmstate description of CPU
  target/riscv: Add PMP state description
  target/riscv: Add H extention state description
  target/riscv: Add V extention state description
  target/riscv: Add sifive_plic vmstate

 hw/intc/sifive_plic.c    |  26 +++++-
 hw/intc/sifive_plic.h    |   1 +
 target/riscv/cpu.c       |   7 --
 target/riscv/cpu.h       |   4 +
 target/riscv/machine.c   | 184 +++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |   3 +-
 6 files changed, 214 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/machine.c

Comments

Richard Henderson Oct. 1, 2020, 5:23 p.m. UTC | #1 
On 9/28/20 9:03 PM, Yifei Jiang wrote:
> --- /dev/null
> +++ b/target/riscv/machine.c
> @@ -0,0 +1,59 @@
> +#include "qemu/osdep.h"
> +#include "cpu.h"

All new files must contain license boilerplate.

Otherwise, considering the followups, this seems ok.


r~
Richard Henderson Oct. 1, 2020, 5:30 p.m. UTC | #2 
On 9/28/20 9:03 PM, Yifei Jiang wrote:
> In the case of supporting V extention, add V extention description
> to vmstate_riscv_cpu.
> 
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/machine.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Though of course this is racing with the v1.0 patch set, which changes the set
of vector csrs.


r~
Jiangyifei Oct. 9, 2020, 8:11 a.m. UTC | #3 
> -----Original Message-----

> From: Richard Henderson [mailto:richard.henderson@linaro.org]

> Sent: Friday, October 2, 2020 1:23 AM

> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;

> qemu-riscv@nongnu.org

> Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>;

> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng

> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng

> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)

> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>

> Subject: Re: [PATCH 1/5] target/riscv: Add basic vmstate description of CPU

> 

> On 9/28/20 9:03 PM, Yifei Jiang wrote:

> > --- /dev/null

> > +++ b/target/riscv/machine.c

> > @@ -0,0 +1,59 @@

> > +#include "qemu/osdep.h"

> > +#include "cpu.h"

> 

> All new files must contain license boilerplate.

> 

> Otherwise, considering the followups, this seems ok.

> 


Thanks, I'll add license boilerplate in the next series.

Yifei

> 

> r~