diff mbox series

[v4,1/3] dt-bindings: dmaengine: Document qcom,gpi dma binding

Message ID 20201008123151.764238-2-vkoul@kernel.org
State Accepted
Commit 678198f21135b0aaf9782049d0a6bbbeefff1804
Headers show
Series [v4,1/3] dt-bindings: dmaengine: Document qcom,gpi dma binding | expand

Commit Message

Vinod Koul Oct. 8, 2020, 12:31 p.m. UTC
Add devicetree binding documentation for GPI DMA controller
implemented on Qualcomm SoCs

Signed-off-by: Vinod Koul <vkoul@kernel.org>

---
 .../devicetree/bindings/dma/qcom,gpi.yaml     | 86 +++++++++++++++++++
 include/dt-bindings/dma/qcom-gpi.h            | 11 +++
 2 files changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/qcom,gpi.yaml
 create mode 100644 include/dt-bindings/dma/qcom-gpi.h

-- 
2.26.2

Comments

Rob Herring (Arm) Oct. 12, 2020, 6:57 p.m. UTC | #1
On Thu, Oct 08, 2020 at 06:01:49PM +0530, Vinod Koul wrote:
> Add devicetree binding documentation for GPI DMA controller

> implemented on Qualcomm SoCs

> 

> Signed-off-by: Vinod Koul <vkoul@kernel.org>

> ---

>  .../devicetree/bindings/dma/qcom,gpi.yaml     | 86 +++++++++++++++++++

>  include/dt-bindings/dma/qcom-gpi.h            | 11 +++

>  2 files changed, 97 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/dma/qcom,gpi.yaml

>  create mode 100644 include/dt-bindings/dma/qcom-gpi.h

> 

> diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml

> new file mode 100644

> index 000000000000..4470c1b2fd6c

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml

> @@ -0,0 +1,86 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: Qualcomm Technologies Inc GPI DMA controller

> +

> +maintainers:

> +  - Vinod Koul <vkoul@kernel.org>

> +

> +description: |

> +  QCOM GPI DMA controller provides DMA capabilities for

> +  peripheral buses such as I2C, UART, and SPI.

> +

> +allOf:

> +  - $ref: "dma-controller.yaml#"

> +

> +properties:

> +  compatible:

> +    enum:

> +      - qcom,sdm845-gpi-dma

> +

> +  reg:

> +    maxItems: 1

> +

> +  interrupts:

> +    description:

> +      Interrupt lines for each GPI instance

> +    maxItems: 13

> +

> +  "#dma-cells":

> +    const: 3

> +    description: >

> +      DMA clients must use the format described in dma.txt, giving a phandle

> +      to the DMA controller plus the following 3 integer cells:

> +      - channel: if set to 0xffffffff, any available channel will be allocated

> +        for the client. Otherwise, the exact channel specified will be used.

> +      - seid: serial id of the client as defined in the SoC documentation.

> +      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h

> +

> +  iommus:

> +    maxItems: 1

> +

> +  dma-channels:

> +    maximum: 31

> +

> +  dma-channel-mask:

> +    maxItems: 1

> +

> +required:

> +  - compatible

> +  - reg

> +  - interrupts

> +  - "#dma-cells"

> +  - iommus

> +  - dma-channels

> +  - dma-channel-mask


additionalProperties: false

With that,

Reviewed-by: Rob Herring <robh@kernel.org>


> +

> +examples:

> +  - |

> +    #include <dt-bindings/interrupt-controller/arm-gic.h>

> +    #include <dt-bindings/dma/qcom-gpi.h>

> +    gpi_dma0: dma-controller@800000 {

> +        compatible = "qcom,gpi-dma";

> +        #dma-cells = <3>;

> +        reg = <0x00800000 0x60000>;

> +        iommus = <&apps_smmu 0x0016 0x0>;

> +        dma-channels = <13>;

> +        dma-channel-mask = <0xfa>;

> +        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

> +                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;

> +    };

> +

> +...

> diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h

> new file mode 100644

> index 000000000000..71f79eb7614c

> --- /dev/null

> +++ b/include/dt-bindings/dma/qcom-gpi.h

> @@ -0,0 +1,11 @@

> +/* SPDX-License-Identifier: GPL-2.0 */

> +/* Copyright (c) 2020, Linaro Ltd.  */

> +

> +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__

> +#define __DT_BINDINGS_DMA_QCOM_GPI_H__

> +

> +#define QCOM_GPI_SPI		1

> +#define QCOM_GPI_UART		2

> +#define QCOM_GPI_I2C		3

> +

> +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */

> -- 

> 2.26.2

>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
new file mode 100644
index 000000000000..4470c1b2fd6c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -0,0 +1,86 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies Inc GPI DMA controller
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+description: |
+  QCOM GPI DMA controller provides DMA capabilities for
+  peripheral buses such as I2C, UART, and SPI.
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdm845-gpi-dma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description:
+      Interrupt lines for each GPI instance
+    maxItems: 13
+
+  "#dma-cells":
+    const: 3
+    description: >
+      DMA clients must use the format described in dma.txt, giving a phandle
+      to the DMA controller plus the following 3 integer cells:
+      - channel: if set to 0xffffffff, any available channel will be allocated
+        for the client. Otherwise, the exact channel specified will be used.
+      - seid: serial id of the client as defined in the SoC documentation.
+      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
+
+  iommus:
+    maxItems: 1
+
+  dma-channels:
+    maximum: 31
+
+  dma-channel-mask:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#dma-cells"
+  - iommus
+  - dma-channels
+  - dma-channel-mask
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/dma/qcom-gpi.h>
+    gpi_dma0: dma-controller@800000 {
+        compatible = "qcom,gpi-dma";
+        #dma-cells = <3>;
+        reg = <0x00800000 0x60000>;
+        iommus = <&apps_smmu 0x0016 0x0>;
+        dma-channels = <13>;
+        dma-channel-mask = <0xfa>;
+        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+    };
+
+...
diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h
new file mode 100644
index 000000000000..71f79eb7614c
--- /dev/null
+++ b/include/dt-bindings/dma/qcom-gpi.h
@@ -0,0 +1,11 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2020, Linaro Ltd.  */
+
+#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
+#define __DT_BINDINGS_DMA_QCOM_GPI_H__
+
+#define QCOM_GPI_SPI		1
+#define QCOM_GPI_UART		2
+#define QCOM_GPI_I2C		3
+
+#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */