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[0/3] crypto: Add Keem Bay OCS HCU driver

Message ID 20201016172759.1260407-1-daniele.alessandrelli@linux.intel.com
Headers show
Series crypto: Add Keem Bay OCS HCU driver | expand

Message

Daniele Alessandrelli Oct. 16, 2020, 5:27 p.m. UTC
The Intel Keem Bay SoC has an Offload Crypto Subsystem (OCS) featuring a
Hashing Control Unit (HCU) for accelerating hashing operations.

This driver adds support for such hardware thus enabling hardware-accelerated
hashing on the Keem Bay SoC for the following algorithms:
- sha224 and hmac(sha224)
- sha256 and hmac(sha256)
- sha384 and hmac(sha384)
- sha512 and hmac(sha512)
- sm3    and hmac(sm3)

The driver is passing crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).


Daniele Alessandrelli (1):
  MAINTAINERS: Add maintainers for Keem Bay OCS HCU driver

Declan Murphy (2):
  dt-bindings: crypto: Add Keem Bay OCS HCU bindings
  crypto: keembay: Add Keem Bay OCS HCU driver

 .../crypto/intel,keembay-ocs-hcu.yaml         |   52 +
 MAINTAINERS                                   |   11 +
 drivers/crypto/Kconfig                        |    2 +
 drivers/crypto/Makefile                       |    1 +
 drivers/crypto/keembay/Kconfig                |   23 +
 drivers/crypto/keembay/Makefile               |    5 +
 drivers/crypto/keembay/keembay-ocs-hcu-core.c | 1473 +++++++++++++++++
 drivers/crypto/keembay/ocs-hcu.c              |  590 +++++++
 drivers/crypto/keembay/ocs-hcu.h              |  113 ++
 9 files changed, 2270 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
 create mode 100644 drivers/crypto/keembay/Kconfig
 create mode 100644 drivers/crypto/keembay/Makefile
 create mode 100644 drivers/crypto/keembay/keembay-ocs-hcu-core.c
 create mode 100644 drivers/crypto/keembay/ocs-hcu.c
 create mode 100644 drivers/crypto/keembay/ocs-hcu.h


base-commit: 3093e7c16e12d729c325adb3c53dde7308cefbd8

Comments

Rob Herring (Arm) Oct. 26, 2020, 1:17 p.m. UTC | #1
On Fri, Oct 16, 2020 at 06:27:57PM +0100, Daniele Alessandrelli wrote:
> From: Declan Murphy <declan.murphy@intel.com>

> 

> Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem

> (OCS) Hashing Control Unit (HCU) crypto driver.

> 

> Signed-off-by: Declan Murphy <declan.murphy@intel.com>

> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

> Acked-by: Mark Gross <mgross@linux.intel.com>

> ---

>  .../crypto/intel,keembay-ocs-hcu.yaml         | 52 +++++++++++++++++++

>  1 file changed, 52 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml

> 

> diff --git a/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml

> new file mode 100644

> index 000000000000..dd4b82ee872b

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml

> @@ -0,0 +1,52 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: Intel Keem Bay OCS HCU Device Tree Bindings

> +

> +maintainers:

> +  - Declan Murphy <declan.murphy@intel.com>

> +  - Daniele Alessandrelli <deniele.alessandrelli@intel.com>


typo:                          ^?

> +

> +description: |


Can drop '|' if there's no formatting to preserve.

> +  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)

> +  crypto driver enables use of the hardware accelerated hashing module embedded

> +  in the Intel Movidius SoC code name Keem Bay, via the kernel crypto API.


Don't put Linux details in bindings. Describe the h/w, not a driver.

> +

> +properties:

> +  compatible:

> +    const: intel,keembay-ocs-hcu

> +

> +  reg:

> +    items:

> +      - description: The OCS HCU base register address

> +

> +  interrupts:

> +    items:

> +      - description: OCS HCU interrupt

> +

> +  clocks:

> +    items:

> +      - description: OCS clock

> +

> +required:

> +  - compatible

> +  - reg

> +  - interrupts

> +  - clocks

> +

> +additionalProperties: false

> +

> +examples:

> +  - |

> +    #include <dt-bindings/interrupt-controller/arm-gic.h>

> +    hcu@3000b000 {


crypto@...

> +      compatible = "intel,keembay-ocs-hcu";

> +      reg = <0x3000b000 0x1000>;

> +      interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

> +      clocks = <&scmi_clk 94>;

> +    };

> +

> +...

> -- 

> 2.26.2

>