| Message ID | 1610306582-16641-1-git-send-email-stefanc@marvell.com |
|---|---|
| State | New |
| Headers | show |
| Series | [net] net: mvpp2: Remove Pause and Asym_Pause support | expand |
niedz., 10 sty 2021 o 20:25 <stefanc@marvell.com> napisał(a): > > From: Stefan Chulski <stefanc@marvell.com> > > Packet Processor hardware not connected to MAC flow control unit and > cannot support TX flow control. > This patch disable flow control support. > > Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index 82c6bef..d04171d 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -5861,8 +5861,6 @@ static void mvpp2_phylink_validate(struct phylink_config *config, > > phylink_set(mask, Autoneg); > phylink_set_port_modes(mask); > - phylink_set(mask, Pause); > - phylink_set(mask, Asym_Pause); > > switch (state->interface) { > case PHY_INTERFACE_MODE_10GBASER: > -- > 1.9.1 > Acked-by: Marcin Wojtas <mw@semihalf.com> Thanks!
On Sun, 10 Jan 2021 21:23:02 +0200 stefanc@marvell.com wrote: > From: Stefan Chulski <stefanc@marvell.com> > > Packet Processor hardware not connected to MAC flow control unit and > cannot support TX flow control. > This patch disable flow control support. > > Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") > Signed-off-by: Stefan Chulski <stefanc@marvell.com> I'm probably missing something, but why not 4bb043262878 ("net: mvpp2: phylink support")?
On Mon, Jan 11, 2021 at 04:36:53PM -0800, Jakub Kicinski wrote: > On Sun, 10 Jan 2021 21:23:02 +0200 stefanc@marvell.com wrote: > > From: Stefan Chulski <stefanc@marvell.com> > > > > Packet Processor hardware not connected to MAC flow control unit and > > cannot support TX flow control. > > This patch disable flow control support. > > > > Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > > I'm probably missing something, but why not 4bb043262878 ("net: mvpp2: > phylink support")? Hi Jakub Before that change, it used phylib. The same is true with phylib, you need to tell phylib it should not advertise pause. How you do it is different, but the basic issue is the same. Anybody doing a backport past 4bb043262878is going to need a different fix, but the basic issue is there all the way back to when the driver was added. Andrew
On Tue, 12 Jan 2021 01:47:27 +0100 Andrew Lunn wrote: > On Mon, Jan 11, 2021 at 04:36:53PM -0800, Jakub Kicinski wrote: > > On Sun, 10 Jan 2021 21:23:02 +0200 stefanc@marvell.com wrote: > > > From: Stefan Chulski <stefanc@marvell.com> > > > > > > Packet Processor hardware not connected to MAC flow control unit and > > > cannot support TX flow control. > > > This patch disable flow control support. > > > > > > Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") > > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > > > > I'm probably missing something, but why not 4bb043262878 ("net: mvpp2: > > phylink support")? > > Hi Jakub > > Before that change, it used phylib. The same is true with phylib, you > need to tell phylib it should not advertise pause. How you do it is > different, but the basic issue is the same. Anybody doing a backport > past 4bb043262878is going to need a different fix, but the basic issue > is there all the way back to when the driver was added. Thanks for confirming, I didn't see any code being removed which would tell phylib pause is supported, so I wanted to make sure phylib defaults to on / gets it from some register. Applied now, thanks!
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 82c6bef..d04171d 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -5861,8 +5861,6 @@ static void mvpp2_phylink_validate(struct phylink_config *config, phylink_set(mask, Autoneg); phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); switch (state->interface) { case PHY_INTERFACE_MODE_10GBASER: