| Message ID | 20210519143700.27392-1-bhupesh.sharma@linaro.org |
|---|---|
| Headers | show |
| Series | Enable Qualcomm Crypto Engine on sm8250 | expand |
Hi Bhupesh, On 5/19/21 10:36 AM, Bhupesh Sharma wrote: > From: Thara Gopinath <thara.gopinath@linaro.org> > > On certain Snapdragon processors, the crypto engine clocks are enabled by > default by security firmware and the driver need not handle the > clocks. Make acquiring of all the clocks optional in crypto enginer driver > so that the driver intializes properly even if no clocks are specified in > the dt. > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Andy Gross <agross@kernel.org> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: David S. Miller <davem@davemloft.net> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: dmaengine@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-crypto@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: bhupesh.linux@gmail.com > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> > [ bhupesh.sharma@linaro.org: Make clock enablement optional only for qcom parts where > firmware has already initialized them, using a bool variable and fix > error paths ] > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > drivers/crypto/qce/core.c | 89 +++++++++++++++++++++++++-------------- > drivers/crypto/qce/core.h | 2 + > 2 files changed, 59 insertions(+), 32 deletions(-) > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > index 905378906ac7..8c3c68ba579e 100644 > --- a/drivers/crypto/qce/core.c > +++ b/drivers/crypto/qce/core.c > @@ -9,6 +9,7 @@ > #include <linux/interrupt.h> > #include <linux/module.h> > #include <linux/mod_devicetable.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/spinlock.h> > #include <linux/types.h> > @@ -184,10 +185,20 @@ static int qce_check_version(struct qce_device *qce) > return 0; > } > > +static const struct of_device_id qce_crypto_of_match[] = { > + { .compatible = "qcom,ipq6018-qce", }, > + { .compatible = "qcom,sdm845-qce", }, > + { .compatible = "qcom,sm8250-qce", }, Adding qcom,sm8250-qce does not belong in this patch. It deserves a separate patch of it's own. > + {} > +}; > +MODULE_DEVICE_TABLE(of, qce_crypto_of_match); > + > static int qce_crypto_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct qce_device *qce; > + const struct of_device_id *of_id = > + of_match_device(qce_crypto_of_match, &pdev->dev); > int ret; > > qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); > @@ -198,45 +209,65 @@ static int qce_crypto_probe(struct platform_device *pdev) > platform_set_drvdata(pdev, qce); > > qce->base = devm_platform_ioremap_resource(pdev, 0); > - if (IS_ERR(qce->base)) > - return PTR_ERR(qce->base); > + if (IS_ERR(qce->base)) { > + ret = PTR_ERR(qce->base); > + goto err_out; > + } I don't see the reason for change in error handling here or below. But ,for whatever reason this is changed, it has to be a separate patch. > > ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); > if (ret < 0) > - return ret; > + goto err_out; > > qce->mem_path = devm_of_icc_get(qce->dev, "memory"); > if (IS_ERR(qce->mem_path)) > return dev_err_probe(dev, PTR_ERR(qce->mem_path), > "Failed to get mem path\n"); > > - qce->core = devm_clk_get(qce->dev, "core"); > - if (IS_ERR(qce->core)) > - return PTR_ERR(qce->core); > - > - qce->iface = devm_clk_get(qce->dev, "iface"); > - if (IS_ERR(qce->iface)) > - return PTR_ERR(qce->iface); > - > - qce->bus = devm_clk_get(qce->dev, "bus"); > - if (IS_ERR(qce->bus)) > - return PTR_ERR(qce->bus); > - > ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); > if (ret) > - return ret; > + goto err_out; > > - ret = clk_prepare_enable(qce->core); > - if (ret) > - return ret; > + /* On some qcom parts the crypto clocks are already configured by > + * the firmware running before linux. In such cases we don't need to > + * enable/configure them again. Check here for the same. > + */ > + if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") || > + !strcmp(of_id->compatible, "qcom,sdm845-qce")) You can avoid this and most of this patch by using devm_clk_get_optional. This patch can be like just three lines of code change. clk_prepare_enable returns 0 if the clock is null. There is no need to check for the compatibles above. Use devm_clk_get_optional instead of devm_clk_get and everything else can be left as is. Warm Regards Thara > + qce->clks_configured_by_fw = false; > + else > + qce->clks_configured_by_fw = true; > + > + if (!qce->clks_configured_by_fw) { > + qce->core = devm_clk_get(qce->dev, "core"); > + if (IS_ERR(qce->core)) { > + ret = PTR_ERR(qce->core); > + goto err_out; > + } > + > + qce->iface = devm_clk_get(qce->dev, "iface"); > + if (IS_ERR(qce->iface)) { > + ret = PTR_ERR(qce->iface); > + goto err_out; > + } > + > + qce->bus = devm_clk_get(qce->dev, "bus"); > + if (IS_ERR(qce->bus)) { > + ret = PTR_ERR(qce->bus); > + goto err_out; > + } > + > + ret = clk_prepare_enable(qce->core); > + if (ret) > + goto err_out; > > - ret = clk_prepare_enable(qce->iface); > - if (ret) > - goto err_clks_core; > + ret = clk_prepare_enable(qce->iface); > + if (ret) > + goto err_clks_core; > > - ret = clk_prepare_enable(qce->bus); > - if (ret) > - goto err_clks_iface; > + ret = clk_prepare_enable(qce->bus); > + if (ret) > + goto err_clks_iface; > + } > > ret = qce_dma_request(qce->dev, &qce->dma); > if (ret) > @@ -268,6 +299,7 @@ static int qce_crypto_probe(struct platform_device *pdev) > clk_disable_unprepare(qce->iface); > err_clks_core: > clk_disable_unprepare(qce->core); > +err_out: > return ret; > } > > @@ -284,13 +316,6 @@ static int qce_crypto_remove(struct platform_device *pdev) > return 0; > } > > -static const struct of_device_id qce_crypto_of_match[] = { > - { .compatible = "qcom,ipq6018-qce", }, > - { .compatible = "qcom,sdm845-qce", }, > - {} > -}; > -MODULE_DEVICE_TABLE(of, qce_crypto_of_match); > - > static struct platform_driver qce_crypto_driver = { > .probe = qce_crypto_probe, > .remove = qce_crypto_remove, > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h > index 228fcd69ec51..d9bf05babecc 100644 > --- a/drivers/crypto/qce/core.h > +++ b/drivers/crypto/qce/core.h > @@ -23,6 +23,7 @@ > * @dma: pointer to dma data > * @burst_size: the crypto burst size > * @pipe_pair_id: which pipe pair id the device using > + * @clks_configured_by_fw: clocks are already configured by fw > * @async_req_enqueue: invoked by every algorithm to enqueue a request > * @async_req_done: invoked by every algorithm to finish its request > */ > @@ -39,6 +40,7 @@ struct qce_device { > struct qce_dma_data dma; > int burst_size; > unsigned int pipe_pair_id; > + bool clks_configured_by_fw; > int (*async_req_enqueue)(struct qce_device *qce, > struct crypto_async_request *req); > void (*async_req_done)(struct qce_device *qce, int ret); >
Hi Stephen, On Wed, 2 Jun 2021 at 12:54, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Bhupesh Sharma (2021-05-19 07:36:43) > > > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Andy Gross <agross@kernel.org> > > Cc: Herbert Xu <herbert@gondor.apana.org.au> > > Cc: David S. Miller <davem@davemloft.net> > > Cc: Stephen Boyd <sboyd@kernel.org> > > Cc: Michael Turquette <mturquette@baylibre.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: dmaengine@vger.kernel.org > > Cc: linux-clk@vger.kernel.org > > Can you stop Cc-ing the clk list? It puts it into my review queue when > as far as I can tell there isn't anything really clk related to review > here. Or do you need an ack on something? Sure, I will drop the clk-list from Cc-list of future patchset versions. Since I had a couple of clk driver changes in v1 which were dropped starting from v2, I thought it would be good to Cc clk-list for v2 (and so on..) Thanks, Bhupesh
Changes since v2: ================= - v2 can be seen here: https://lore.kernel.org/dmaengine/20210505213731.538612-1-bhupesh.sharma@linaro.org/ - Drop a couple of patches from v1, which tried to address the defered probing of qce driver in case bam dma driver is not yet probed. Replace it instead with a single (simpler) patch [PATCH 16/17]. - Convert bam dma and qce crypto dt-bindings to YAML. - Addressed review comments from Thara, Bjorn, Vinod and Rob. Changes since v1: ================= - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20210310052503.3618486-1-bhupesh.sharma@linaro.org/ - v1 did not work well as reported earlier by Dmitry, so v2 contains the following changes/fixes: ~ Enable the interconnect path b/w BAM DMA and main memory first before trying to access the BAM DMA registers. ~ Enable the interconnect path b/w qce crytpo and main memory first before trying to access the qce crypto registers. ~ Make sure to document the required and optional properties for both BAM DMA and qce crypto drivers. ~ Add a few debug related print messages in case the qce crypto driver passes or fails to probe. ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA or the interconnect driver(s) (needed on specific Qualcomm parts) are not yet probed. Qualcomm crypto engine is also available on sm8250 SoC. It supports hardware accelerated algorithms for encryption and authentication. It also provides support for aes, des, 3des encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256) authentication algorithms. Tested the enabled crypto algorithms with cryptsetup test utilities on sm8250-mtp and RB5 board (see [1]) and also with crypto self-tests, including the fuzz tests (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y). While at it, also make a minor fix in 'sdm845.dtsi', to make sure it confirms with the other .dtsi files which expose crypto nodes on qcom SoCs. Note that this series is rebased on AEAD fixes from Thara (see [2]). This is required for all of the fuzz tests to work. [1]. https://linux.die.net/man/8/cryptsetup [2]. https://lore.kernel.org/linux-crypto/20210429150707.3168383-5-thara.gopinath@linaro.org/T/ Cc: Thara Gopinath <thara.gopinath@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: David S. Miller <davem@davemloft.net> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Bhupesh Sharma (14): dt-bindings: qcom-bam: Convert binding to YAML dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties dt-bindings: qcom-bam: Add 'iommus' to required properties dt-bindings: qcom-qce: Convert bindings to yaml dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties dt-bindings: qcom-qce: Add 'iommus' to required properties arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly dt-bindings: crypto : Add new compatible strings for qcom-qce arm64/dts: qcom: Use new compatibles for crypto nodes crypto: qce: Add new compatibles for qce crypto driver crypto: qce: Print a failure msg in case probe() fails crypto: qce: Convert the device found dev_dbg() to dev_info() crypto: qce: Defer probing if BAM dma channel is not yet initialized arm64/dts: qcom: sm8250: Add dt entries to support crypto engine. Thara Gopinath (3): dma: qcom: bam_dma: Add support to initialize interconnect path crypto: qce: core: Add support to initialize interconnect path crypto: qce: core: Make clocks optional .../devicetree/bindings/crypto/qcom-qce.txt | 25 ---- .../devicetree/bindings/crypto/qcom-qce.yaml | 92 +++++++++++++++ .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 -------- .../devicetree/bindings/dma/qcom_bam_dma.yaml | 110 ++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 +++++ drivers/crypto/qce/core.c | 110 ++++++++++++------ drivers/crypto/qce/core.h | 3 + drivers/dma/qcom/bam_dma.c | 10 ++ 10 files changed, 322 insertions(+), 114 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml