| Message ID | 20210715121209.31024-1-yong.wu@mediatek.com |
|---|---|
| Headers | show |
| Series | MT8195 SMI support | expand |
On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > Use clk_bulk interface instead of the orginal one to simplify the code. > > SMI have several clocks: apb/smi/gals, the apb/smi clocks are required > for both smi-common and smi-larb while the gals clock are optional. > thus, use devm_clk_bulk_get for apb/smi and use > devm_clk_bulk_get_optional for gals. > > For gals clocks, we already use get_optional for it, then the flag > "has_gals" is not helpful now, remove it. > > Also remove clk fail logs since bulk interface already output fail log. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> > --- > drivers/memory/mtk-smi.c | 138 +++++++++++++-------------------------- > 1 file changed, 47 insertions(+), 91 deletions(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index c5fb51f73b34..a2213452059d 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -60,9 +60,15 @@ enum mtk_smi_gen { > MTK_SMI_GEN2 > }; > > +#define MTK_SMI_CLK_NR_MAX 4 > + > +/* Always require apb/smi clocks while gals clocks are optional. */ > +static const char * const mtk_smi_clks_required[] = {"apb", "smi"}; > +static const char * const mtk_smi_common_clks_optional[] = {"gals0", "gals1"}; > +static const char * const mtk_smi_larb_clks_optional[] = {"gals"}; > + > struct mtk_smi_common_plat { > enum mtk_smi_gen gen; > - bool has_gals; > u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ > }; > > @@ -70,13 +76,12 @@ struct mtk_smi_larb_gen { > int port_in_larb[MTK_LARB_NR_MAX + 1]; > void (*config_port)(struct device *dev); > unsigned int larb_direct_to_common_mask; > - bool has_gals; > }; > > struct mtk_smi { > struct device *dev; > - struct clk *clk_apb, *clk_smi; > - struct clk *clk_gals0, *clk_gals1; > + unsigned int clk_num; > + struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; > struct clk *clk_async; /*only needed by mt2701*/ > union { > void __iomem *smi_ao_base; /* only for gen1 */ > @@ -95,45 +100,6 @@ struct mtk_smi_larb { /* larb: local arbiter */ > unsigned char *bank; > }; > > -static int mtk_smi_clk_enable(const struct mtk_smi *smi) > -{ > - int ret; > - > - ret = clk_prepare_enable(smi->clk_apb); > - if (ret) > - return ret; > - > - ret = clk_prepare_enable(smi->clk_smi); > - if (ret) > - goto err_disable_apb; > - > - ret = clk_prepare_enable(smi->clk_gals0); > - if (ret) > - goto err_disable_smi; > - > - ret = clk_prepare_enable(smi->clk_gals1); > - if (ret) > - goto err_disable_gals0; > - > - return 0; > - > -err_disable_gals0: > - clk_disable_unprepare(smi->clk_gals0); > -err_disable_smi: > - clk_disable_unprepare(smi->clk_smi); > -err_disable_apb: > - clk_disable_unprepare(smi->clk_apb); > - return ret; > -} > - > -static void mtk_smi_clk_disable(const struct mtk_smi *smi) > -{ > - clk_disable_unprepare(smi->clk_gals1); > - clk_disable_unprepare(smi->clk_gals0); > - clk_disable_unprepare(smi->clk_smi); > - clk_disable_unprepare(smi->clk_apb); > -} > - > int mtk_smi_larb_get(struct device *larbdev) > { > int ret = pm_runtime_resume_and_get(larbdev); > @@ -270,7 +236,6 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { > }; > > static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { > - .has_gals = true, > .config_port = mtk_smi_larb_config_port_gen2_general, > .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), > /* IPU0 | IPU1 | CCU */ > @@ -312,6 +277,27 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { > {} > }; > > +static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, > + unsigned int clk_nr_optional, > + const char * const clk_optional[]) > +{ > + int i, ret, clk_nr_required; > + > + clk_nr_required = ARRAY_SIZE(mtk_smi_clks_required); > + for (i = 0; i < clk_nr_required; i++) > + smi->clks[i].id = mtk_smi_clks_required[i]; > + ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); > + if (ret) > + return ret; > + > + for (i = 0; i < clk_nr_optional; i++) > + smi->clks[i + clk_nr_required].id = clk_optional[i]; > + ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, > + smi->clks + clk_nr_required); > + smi->clk_num = clk_nr_required + clk_nr_optional; > + return ret; > +} > + > static int mtk_smi_larb_probe(struct platform_device *pdev) > { > struct mtk_smi_larb *larb; > @@ -320,6 +306,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) > struct device_node *smi_node; > struct platform_device *smi_pdev; > struct device_link *link; > + int ret; > > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); > if (!larb) > @@ -331,24 +318,13 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) > if (IS_ERR(larb->base)) > return PTR_ERR(larb->base); > > - larb->smi.clk_apb = devm_clk_get(dev, "apb"); > - if (IS_ERR(larb->smi.clk_apb)) > - return PTR_ERR(larb->smi.clk_apb); > - > - larb->smi.clk_smi = devm_clk_get(dev, "smi"); > - if (IS_ERR(larb->smi.clk_smi)) > - return PTR_ERR(larb->smi.clk_smi); > - > - if (larb->larb_gen->has_gals) { > - /* The larbs may still haven't gals even if the SoC support.*/ > - larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); > - if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) > - larb->smi.clk_gals0 = NULL; > - else if (IS_ERR(larb->smi.clk_gals0)) > - return PTR_ERR(larb->smi.clk_gals0); > - } > - larb->smi.dev = dev; > + ret = mtk_smi_dts_clk_init(dev, &larb->smi, > + ARRAY_SIZE(mtk_smi_larb_clks_optional), > + mtk_smi_larb_clks_optional); > + if (ret) > + return ret; > > + larb->smi.dev = dev; > smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); > if (!smi_node) > return -EINVAL; > @@ -391,11 +367,9 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev) > const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; > int ret; > > - ret = mtk_smi_clk_enable(&larb->smi); > - if (ret < 0) { > - dev_err(dev, "Failed to enable clock(%d).\n", ret); > + ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); > + if (ret < 0) > return ret; > - } > > /* Configure the basic setting for this larb */ > larb_gen->config_port(dev); > @@ -407,7 +381,7 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > - mtk_smi_clk_disable(&larb->smi); > + clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); > return 0; > } > > @@ -437,21 +411,18 @@ static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { > > static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { > .gen = MTK_SMI_GEN2, > - .has_gals = true, > .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | > F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), > }; > > static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { > .gen = MTK_SMI_GEN2, > - .has_gals = true, > .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | > F_MMU1_LARB(7), > }; > > static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { > .gen = MTK_SMI_GEN2, > - .has_gals = true, > .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | > F_MMU1_LARB(6), > }; > @@ -501,23 +472,10 @@ static int mtk_smi_common_probe(struct platform_device *pdev) > common->dev = dev; > common->plat = of_device_get_match_data(dev); > > - common->clk_apb = devm_clk_get(dev, "apb"); > - if (IS_ERR(common->clk_apb)) > - return PTR_ERR(common->clk_apb); > - > - common->clk_smi = devm_clk_get(dev, "smi"); > - if (IS_ERR(common->clk_smi)) > - return PTR_ERR(common->clk_smi); > - > - if (common->plat->has_gals) { > - common->clk_gals0 = devm_clk_get(dev, "gals0"); > - if (IS_ERR(common->clk_gals0)) > - return PTR_ERR(common->clk_gals0); > - > - common->clk_gals1 = devm_clk_get(dev, "gals1"); > - if (IS_ERR(common->clk_gals1)) > - return PTR_ERR(common->clk_gals1); > - } > + ret = mtk_smi_dts_clk_init(dev, common, ARRAY_SIZE(mtk_smi_common_clks_optional), > + mtk_smi_common_clks_optional); > + if (ret) > + return ret; > > /* > * for mtk smi gen 1, we need to get the ao(always on) base to config > @@ -561,11 +519,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > u32 bus_sel = common->plat->bus_sel; > int ret; > > - ret = mtk_smi_clk_enable(common); > - if (ret) { > - dev_err(common->dev, "Failed to enable clock(%d).\n", ret); > + ret = clk_bulk_prepare_enable(common->clk_num, common->clks); > + if (ret) > return ret; > - } > > if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) > writel(bus_sel, common->base + SMI_BUS_SEL); > @@ -576,7 +532,7 @@ static int __maybe_unused mtk_smi_common_suspend(struct device *dev) > { > struct mtk_smi *common = dev_get_drvdata(dev); > > - mtk_smi_clk_disable(common); > + clk_bulk_disable_unprepare(common->clk_num, common->clks); > return 0; > } > > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > No functional change. Only move the code position to make the code more > readable. > 1. Put the register smi-common above smi-larb. Prepare to add some others > register setting. > 2. Put mtk_smi_larb_unbind around larb_bind. > 3. Sort the SoC data alphabetically. and put them in one line as the > current kernel allow it. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> > --- > drivers/memory/mtk-smi.c | 185 +++++++++++++++------------------------ > 1 file changed, 73 insertions(+), 112 deletions(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index ff07b14bcd66..6f8e582bace5 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -17,12 +17,15 @@ > #include <dt-bindings/memory/mt2701-larb-port.h> > #include <dt-bindings/memory/mtk-memory-port.h> > > -/* mt8173 */ > -#define SMI_LARB_MMU_EN 0xf00 > +/* SMI COMMON */ > +#define SMI_BUS_SEL 0x220 > +#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > +/* All are MMU0 defaultly. Only specialize mmu1 here. */ > +#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) > > -/* mt8167 */ > -#define MT8167_SMI_LARB_MMU_EN 0xfc0 > +/* SMI LARB */ > > +/* Below are about mmu enable registers, they are different in SoCs */ > /* mt2701 */ > #define REG_SMI_SECUR_CON_BASE 0x5c0 > > @@ -41,20 +44,20 @@ > /* mt2701 domain should be set to 3 */ > #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) > > -/* mt2712 */ > -#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) > -#define F_MMU_EN BIT(0) > -#define BANK_SEL(id) ({ \ > +/* mt8167 */ > +#define MT8167_SMI_LARB_MMU_EN 0xfc0 > + > +/* mt8173 */ > +#define MT8173_SMI_LARB_MMU_EN 0xf00 > + > +/* larb gen2 */ > +#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) > +#define F_MMU_EN BIT(0) > +#define BANK_SEL(id) ({ \ > u32 _id = (id) & 0x3; \ > (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ > }) > > -/* SMI COMMON */ > -#define SMI_BUS_SEL 0x220 > -#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > -/* All are MMU0 defaultly. Only specialize mmu1 here. */ > -#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) > - > enum mtk_smi_type { > MTK_SMI_GEN1, > MTK_SMI_GEN2 > @@ -132,36 +135,16 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) > return -ENODEV; > } > > -static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > -{ > - struct mtk_smi_larb *larb = dev_get_drvdata(dev); > - u32 reg; > - int i; > - > - if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > - return; > - > - for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > - reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > - reg |= F_MMU_EN; > - reg |= BANK_SEL(larb->bank[i]); > - writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > - } > -} > - > -static void mtk_smi_larb_config_port_mt8173(struct device *dev) > +static void > +mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) > { > - struct mtk_smi_larb *larb = dev_get_drvdata(dev); > - > - writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); > + /* Do nothing as the iommu is always enabled. */ > } > > -static void mtk_smi_larb_config_port_mt8167(struct device *dev) > -{ > - struct mtk_smi_larb *larb = dev_get_drvdata(dev); > - > - writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); > -} > +static const struct component_ops mtk_smi_larb_component_ops = { > + .bind = mtk_smi_larb_bind, > + .unbind = mtk_smi_larb_unbind, > +}; > > static void mtk_smi_larb_config_port_gen1(struct device *dev) > { > @@ -194,26 +177,36 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > } > } > > -static void > -mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) > +static void mtk_smi_larb_config_port_mt8167(struct device *dev) > { > - /* Do nothing as the iommu is always enabled. */ > + struct mtk_smi_larb *larb = dev_get_drvdata(dev); > + > + writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); > } > > -static const struct component_ops mtk_smi_larb_component_ops = { > - .bind = mtk_smi_larb_bind, > - .unbind = mtk_smi_larb_unbind, > -}; > +static void mtk_smi_larb_config_port_mt8173(struct device *dev) > +{ > + struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > -static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { > - /* mt8173 do not need the port in larb */ > - .config_port = mtk_smi_larb_config_port_mt8173, > -}; > + writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); > +} > > -static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { > - /* mt8167 do not need the port in larb */ > - .config_port = mtk_smi_larb_config_port_mt8167, > -}; > +static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > +{ > + struct mtk_smi_larb *larb = dev_get_drvdata(dev); > + u32 reg; > + int i; > + > + if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > + return; > + > + for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > + reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > + reg |= F_MMU_EN; > + reg |= BANK_SEL(larb->bank[i]); > + writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > + } > +} > > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { > .port_in_larb = { > @@ -235,6 +228,16 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { > /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ > }; > > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { > + /* mt8167 do not need the port in larb */ > + .config_port = mtk_smi_larb_config_port_mt8167, > +}; > + > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { > + /* mt8173 do not need the port in larb */ > + .config_port = mtk_smi_larb_config_port_mt8173, > +}; > + > static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { > .config_port = mtk_smi_larb_config_port_gen2_general, > .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), > @@ -246,34 +249,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { > }; > > static const struct of_device_id mtk_smi_larb_of_ids[] = { > - { > - .compatible = "mediatek,mt8167-smi-larb", > - .data = &mtk_smi_larb_mt8167 > - }, > - { > - .compatible = "mediatek,mt8173-smi-larb", > - .data = &mtk_smi_larb_mt8173 > - }, > - { > - .compatible = "mediatek,mt2701-smi-larb", > - .data = &mtk_smi_larb_mt2701 > - }, > - { > - .compatible = "mediatek,mt2712-smi-larb", > - .data = &mtk_smi_larb_mt2712 > - }, > - { > - .compatible = "mediatek,mt6779-smi-larb", > - .data = &mtk_smi_larb_mt6779 > - }, > - { > - .compatible = "mediatek,mt8183-smi-larb", > - .data = &mtk_smi_larb_mt8183 > - }, > - { > - .compatible = "mediatek,mt8192-smi-larb", > - .data = &mtk_smi_larb_mt8192 > - }, > + {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, > + {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, > + {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, > + {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, > + {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, > + {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, > + {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, > {} > }; > > @@ -428,34 +410,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { > }; > > static const struct of_device_id mtk_smi_common_of_ids[] = { > - { > - .compatible = "mediatek,mt8173-smi-common", > - .data = &mtk_smi_common_gen2, > - }, > - { > - .compatible = "mediatek,mt8167-smi-common", > - .data = &mtk_smi_common_gen2, > - }, > - { > - .compatible = "mediatek,mt2701-smi-common", > - .data = &mtk_smi_common_gen1, > - }, > - { > - .compatible = "mediatek,mt2712-smi-common", > - .data = &mtk_smi_common_gen2, > - }, > - { > - .compatible = "mediatek,mt6779-smi-common", > - .data = &mtk_smi_common_mt6779, > - }, > - { > - .compatible = "mediatek,mt8183-smi-common", > - .data = &mtk_smi_common_mt8183, > - }, > - { > - .compatible = "mediatek,mt8192-smi-common", > - .data = &mtk_smi_common_mt8192, > - }, > + {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, > + {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, > + {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, > + {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, > + {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, > + {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, > + {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, > {} > }; > > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Thu, Jul 15, 2021 at 8:25 PM Yong Wu <yong.wu@mediatek.com> wrote: > > In mt8195, there are some larbs connect with the smi-sub-common, then > connect with smi-common. Not critical but I suggest to describe what is smi-sub-common. e.g. "some larbs are not directly connected to smi-common, they are connected to smi-sub-common which is a bridge(?) interface to..." > > Before we create device link between smi-larb with smi-common. If we have > sub-common, we should use device link the smi-larb and smi-sub-common, > then use device link between the smi-sub-common with smi-common. This is > for enabling clock/power automatically. > > Move the device link code to a new interface for reusing. > > There is no SW extra setting for smi-sub-common. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> > --- > drivers/memory/mtk-smi.c | 75 +++++++++++++++++++++++++++------------- > 1 file changed, 51 insertions(+), 24 deletions(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index e68cbb51dd12..ee49bb50f5f5 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -60,7 +60,8 @@ > > enum mtk_smi_type { > MTK_SMI_GEN1, > - MTK_SMI_GEN2 > + MTK_SMI_GEN2, /* gen2 smi common */ > + MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ > }; > > #define MTK_SMI_CLK_NR_MAX 4 > @@ -90,13 +91,14 @@ struct mtk_smi { > void __iomem *smi_ao_base; /* only for gen1 */ > void __iomem *base; /* only for gen2 */ > }; > + struct device *smi_common_dev; /* for sub common */ > const struct mtk_smi_common_plat *plat; > }; > > struct mtk_smi_larb { /* larb: local arbiter */ > struct mtk_smi smi; > void __iomem *base; > - struct device *smi_common_dev; > + struct device *smi_common_dev; /* common or sub-common dev */ > const struct mtk_smi_larb_gen *larb_gen; > int larbid; > u32 *mmu; > @@ -259,6 +261,38 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { > {} > }; > > +static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) > +{ > + struct platform_device *smi_com_pdev; > + struct device_node *smi_com_node; > + struct device *smi_com_dev; > + struct device_link *link; > + > + smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); > + if (!smi_com_node) > + return -EINVAL; > + > + smi_com_pdev = of_find_device_by_node(smi_com_node); > + of_node_put(smi_com_node); > + if (smi_com_pdev) { > + /* smi common is the supplier, Make sure it is ready before */ > + if (!platform_get_drvdata(smi_com_pdev)) > + return -EPROBE_DEFER; > + smi_com_dev = &smi_com_pdev->dev; > + link = device_link_add(dev, smi_com_dev, > + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); > + if (!link) { > + dev_err(dev, "Unable to link smi-common dev\n"); > + return -ENODEV; > + } > + *com_dev = smi_com_dev; > + } else { > + dev_err(dev, "Failed to get the smi_common device\n"); > + return -EINVAL; > + } > + return 0; > +} > + > static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, > unsigned int clk_nr_optional, > const char * const clk_optional[]) > @@ -285,9 +319,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) > struct mtk_smi_larb *larb; > struct resource *res; > struct device *dev = &pdev->dev; > - struct device_node *smi_node; > - struct platform_device *smi_pdev; > - struct device_link *link; > int ret; > > larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); > @@ -307,26 +338,10 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) > return ret; > > larb->smi.dev = dev; > - smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); > - if (!smi_node) > - return -EINVAL; > > - smi_pdev = of_find_device_by_node(smi_node); > - of_node_put(smi_node); > - if (smi_pdev) { > - if (!platform_get_drvdata(smi_pdev)) > - return -EPROBE_DEFER; > - larb->smi_common_dev = &smi_pdev->dev; > - link = device_link_add(dev, larb->smi_common_dev, > - DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); > - if (!link) { > - dev_err(dev, "Unable to link smi-common dev\n"); > - return -ENODEV; > - } > - } else { > - dev_err(dev, "Failed to get the smi_common device\n"); > - return -EINVAL; > - } > + ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); > + if (ret < 0) > + return ret; > > pm_runtime_enable(dev); > platform_set_drvdata(pdev, larb); > @@ -471,6 +486,14 @@ static int mtk_smi_common_probe(struct platform_device *pdev) > if (IS_ERR(common->base)) > return PTR_ERR(common->base); > } > + > + /* link its smi-common if this is smi-sub-common */ > + if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { > + ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); > + if (ret < 0) > + return ret; > + } > + > pm_runtime_enable(dev); > platform_set_drvdata(pdev, common); > return 0; > @@ -478,6 +501,10 @@ static int mtk_smi_common_probe(struct platform_device *pdev) > > static int mtk_smi_common_remove(struct platform_device *pdev) > { > + struct mtk_smi *common = dev_get_drvdata(&pdev->dev); > + > + if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) > + device_link_remove(&pdev->dev, common->smi_common_dev); > pm_runtime_disable(&pdev->dev); > return 0; > } > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Thu, Jul 15, 2021 at 8:22 PM Yong Wu <yong.wu@mediatek.com> wrote: > > MT8195 has two smi-common, their IP are the same. Only the larbs that > connect with the smi-common are different. thus the bus_sel are different > for the two smi-common. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> > --- > drivers/memory/mtk-smi.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index e5a34b3952a0..3c288716a378 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -250,6 +250,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { > .config_port = mtk_smi_larb_config_port_gen2_general, > }; > > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { > + .config_port = mtk_smi_larb_config_port_gen2_general, > +}; > + > static const struct of_device_id mtk_smi_larb_of_ids[] = { > {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, > {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, > @@ -258,6 +262,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { > {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, > {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, > {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, > + {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, > {} > }; > > @@ -430,6 +435,21 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { > F_MMU1_LARB(6), > }; > > +static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { > + .type = MTK_SMI_GEN2, > + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | > + F_MMU1_LARB(7), > +}; > + > +static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { > + .type = MTK_SMI_GEN2, > + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), > +}; > + > +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { > + .type = MTK_SMI_GEN2_SUB_COMM, > +}; > + > static const struct of_device_id mtk_smi_common_of_ids[] = { > {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, > {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, > @@ -438,6 +458,9 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { > {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, > {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, > {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, > + {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, > + {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, > + {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, > {} > }; > > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > To improve the performance, We add some initial setting for smi larbs. > there are two part: > 1), Each port has the special ostd(outstanding) value in each larb. > 2), Two general setting for each larb. > > In some SoC, this setting maybe changed dynamically for some special case > like 4K, and this initial setting is enough in mt8195. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/memory/mtk-smi.c | 74 +++++++++++++++++++++++++++++++++++++++- > 1 file changed, 73 insertions(+), 1 deletion(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index c52bf02458ff..1d9e67520433 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -32,6 +32,14 @@ > #define SMI_DUMMY 0x444 > > /* SMI LARB */ > +#define SMI_LARB_CMD_THRT_CON 0x24 > +#define SMI_LARB_THRT_EN 0x370256 > + > +#define SMI_LARB_SW_FLAG 0x40 > +#define SMI_LARB_SW_FLAG_1 0x1 > + > +#define SMI_LARB_OSTDL_PORT 0x200 > +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) > > /* Below are about mmu enable registers, they are different in SoCs */ > /* mt2701 */ > @@ -67,6 +75,11 @@ > }) > > #define SMI_COMMON_INIT_REGS_NR 6 > +#define SMI_LARB_PORT_NR_MAX 32 > + > +#define MTK_SMI_FLAG_LARB_THRT_EN BIT(0) > +#define MTK_SMI_FLAG_LARB_SW_FLAG BIT(1) > +#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) > > struct mtk_smi_reg_pair { > unsigned int offset; > @@ -97,6 +110,8 @@ struct mtk_smi_larb_gen { > int port_in_larb[MTK_LARB_NR_MAX + 1]; > void (*config_port)(struct device *dev); > unsigned int larb_direct_to_common_mask; > + unsigned int flags_general; > + const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; > }; > > struct mtk_smi { > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > - u32 reg; > + u32 reg, flags_general = larb->larb_gen->flags_general; > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > int i; > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > return; > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > + > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > + > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() registers at the same offset? or is this unique feature for mt8195? > + > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > reg |= F_MMU_EN; > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > } > } > > +static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { > + [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ > + [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ > + [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ > + [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, > + [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, > + [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, > + [6] = {0x06, 0x01, 0x06, 0x0a,}, > + [7] = {0x0c, 0x0c, 0x12,}, > + [8] = {0x0c, 0x0c, 0x12,}, > + [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, > + 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, > + [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, > + 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, > + 0x0d, 0x06, 0x10, 0x10,}, > + [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, > + [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, > + [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, > + [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, > + 0x01, 0x02, 0x02, 0x08, 0x02,}, > + [15] = {}, > + [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, > + 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, > + [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, > + [18] = {0x12, 0x06, 0x12, 0x06,}, > + [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, > + 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, > + 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, > + [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, > + 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, > + 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, > + [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, > + [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, > + [23] = {0x18, 0x01,}, > + [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, > + 0x01, 0x01,}, > + [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, > + 0x02, 0x01,}, > + [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, > + 0x02, 0x01,}, > + [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, > + 0x02, 0x01,}, > + [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, > +}; > + > static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { > .port_in_larb = { > LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, > @@ -269,6 +339,8 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { > > static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { > .config_port = mtk_smi_larb_config_port_gen2_general, > + .flags_general = MTK_SMI_FLAG_LARB_THRT_EN | MTK_SMI_FLAG_LARB_SW_FLAG, > + .ostd = mtk_smi_larb_mt8195_ostd, > }; > > static const struct of_device_id mtk_smi_larb_of_ids[] = { > -- > 2.18.0 > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Thu, 15 Jul 2021 20:11:59 +0800, Yong Wu wrote: > Add mt8195 smi supporting in the bindings. > > In mt8195, there are two smi-common HW, one is for vdo(video output), > the other is for vpp(video processing pipe). They connect with different > smi-larbs, then some setting(bus_sel) is different. Differentiate them > with the compatible string. > > Something like this: > > IOMMU(VDO) IOMMU(VPP) > | | > SMI_COMMON_VDO SMI_COMMON_VPP > ---------------- ---------------- > | | ... | | ... > larb0 larb2 ... larb1 larb3 ... > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > --- > .../bindings/memory-controllers/mediatek,smi-common.yaml | 6 +++++- > .../bindings/memory-controllers/mediatek,smi-larb.yaml | 3 +++ > 2 files changed, 8 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Hi Ikjoon, Thanks very much for your help reviewing.. On Wed, 2021-07-21 at 19:43 +0800, Ikjoon Jang wrote: > On Thu, Jul 15, 2021 at 8:25 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > In mt8195, there are some larbs connect with the smi-sub-common, then > > connect with smi-common. > > Not critical but I suggest to describe what is smi-sub-common. > e.g. "some larbs are not directly connected to smi-common, > they are connected to smi-sub-common which is a bridge(?) interface to..." OK. I will add some brief description about this sub-common in next version. > > > > > Before we create device link between smi-larb with smi-common. If we have > > sub-common, we should use device link the smi-larb and smi-sub-common, > > then use device link between the smi-sub-common with smi-common. This is > > for enabling clock/power automatically. > > > > Move the device link code to a new interface for reusing. > > > > There is no SW extra setting for smi-sub-common. > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Thanks. > > > --- > > drivers/memory/mtk-smi.c | 75 +++++++++++++++++++++++++++------------- > > 1 file changed, 51 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > index e68cbb51dd12..ee49bb50f5f5 100644 > > --- a/drivers/memory/mtk-smi.c > > +++ b/drivers/memory/mtk-smi.c > > @@ -60,7 +60,8 @@ [snip..]
On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > To improve the performance, We add some initial setting for smi larbs. > > there are two part: > > 1), Each port has the special ostd(outstanding) value in each larb. > > 2), Two general setting for each larb. > > > > In some SoC, this setting maybe changed dynamically for some special case > > like 4K, and this initial setting is enough in mt8195. > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > --- [...] > > struct mtk_smi { > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > { > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > - u32 reg; > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > int i; > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > return; > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > + > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > + > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > registers at the same offset? or is this unique feature for mt8195? All the other Platform's larbs have the same format at the same offset. > > > + > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > reg |= F_MMU_EN; > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > } > > } > > [...]
Hi Ikjoon, Just a ping. On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > there are two part: > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > 2), Two general setting for each larb. > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > like 4K, and this initial setting is enough in mt8195. > > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > > --- > [...] > > > struct mtk_smi { > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > { > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > - u32 reg; > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > int i; > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > return; > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > + > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > + > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > registers at the same offset? or is this unique feature for mt8195? > > All the other Platform's larbs have the same format at the same offset. In this case, Do you have some other further comment? If no, I will keep the current solution for this. Thanks. > > > > > > + > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > reg |= F_MMU_EN; > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > } > > > } > > > > > [...] >
Hi, On Thu, Jul 29, 2021 at 2:41 PM Yong Wu <yong.wu@mediatek.com> wrote: > > Hi Ikjoon, > > Just a ping. > > On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > > there are two part: > > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > > 2), Two general setting for each larb. Honestly, I think nobody outside Mediatek will understand this. Can you please update this to be more generic? Like "Apply default bus settings for mt8195, without this, XXX problems can happen.. "? Or for example, adding brief descriptions on what MTK_SMI_FLAG_LARB_THRT_EN, MTK_SMI_FLAG_LARB_SW_FLAG, and MTK_SMI_FLAG_LARB_SW_FLAG[] are for would be better if it's available. > > > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > > like 4K, and this initial setting is enough in mt8195. > > > > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > > > --- > > [...] > > > > struct mtk_smi { > > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > { > > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > > - u32 reg; > > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > > int i; > > > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > > return; > > > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > > + > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > > + > > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > > registers at the same offset? or is this unique feature for mt8195? > > > > All the other Platform's larbs have the same format at the same offset. > > In this case, Do you have some other further comment? If no, I will keep > the current solution for this. Sorry for the late response, I have no further comments or any objections on here. Please go ahead for v3. I just had no idea on the register definitions and wanted to be sure that newly added register definitions are common to all MTK platforms. Thanks! > > Thanks. > > > > > > > > > > + > > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > > reg |= F_MMU_EN; > > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > } > > > > } > > > > > > > > [...] > > >
This patchset mainly adds SMI support for mt8195. Comparing with the previous version, add two new functions: a) add smi sub common b) add initial setting for smi-common and smi-larb. change note: v2: rebase on v5.14-rc1 1) Adjust clk_bulk flow: use devm_clk_bulk_get for necessary clocks. 2) Add two new little patches: a) use devm_platform_ioremap_resource b) Add error handle for smi_probe v1: https://lore.kernel.org/linux-mediatek/20210616114346.18812-1-yong.wu@mediatek.com/ Yong Wu (11): dt-bindings: memory: mediatek: Add mt8195 smi binding dt-bindings: memory: mediatek: Add mt8195 smi sub common memory: mtk-smi: Use clk_bulk instead of the clk ops memory: mtk-smi: Rename smi_gen to smi_type memory: mtk-smi: Adjust some code position memory: mtk-smi: Add error handle for smi_probe memory: mtk-smi: Add smi sub common support memory: mtk-smi: Use devm_platform_ioremap_resource memory: mtk-smi: mt8195: Add smi support memory: mtk-smi: mt8195: Add initial setting for smi-common memory: mtk-smi: mt8195: Add initial setting for smi-larb .../mediatek,smi-common.yaml | 31 +- .../memory-controllers/mediatek,smi-larb.yaml | 3 + drivers/memory/mtk-smi.c | 572 ++++++++++-------- 3 files changed, 356 insertions(+), 250 deletions(-)