| Message ID | 20220218100403.7028-12-ville.syrjala@linux.intel.com |
|---|---|
| State | Accepted |
| Commit | 17309a4793e9eec966544d4013c5bd0b394f4d0d |
| Headers | show |
| Series | drm: Review of mode copies | expand |
On 2/18/2022 2:03 AM, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Initialize on-stack modes with drm_mode_init() to guarantee > no stack garbage in the list head, or that we aren't copying > over another mode's list head. > > Based on the following cocci script, with manual fixups: > @decl@ > identifier M; > expression E; > @@ > - struct drm_display_mode M = E; > + struct drm_display_mode M; > > @@ > identifier decl.M; > expression decl.E; > statement S, S1; > @@ > struct drm_display_mode M; > ... when != S > + drm_mode_init(&M, &E); > + > S1 > > @@ > expression decl.E; > @@ > - &*E > + E > > Cc: Rob Clark <robdclark@gmail.com> > Cc: Sean Paul <sean@poorly.run> > Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> > Cc: linux-arm-msm@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ddd9d89cd456..e7813c6f7bd9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -248,12 +248,13 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > unsigned long lock_flags; > struct dpu_hw_intf_cfg intf_cfg = { 0 }; > > + drm_mode_init(&mode, &phys_enc->cached_mode); > + > if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { > DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); > return; > } > > - mode = phys_enc->cached_mode; > if (!phys_enc->hw_intf->ops.setup_timing_gen) { > DPU_ERROR("timing engine setup is not supported\n"); > return; > @@ -652,7 +653,9 @@ static int dpu_encoder_phys_vid_get_frame_count( > { > struct intf_status s = {0}; > u32 fetch_start = 0; > - struct drm_display_mode mode = phys_enc->cached_mode; > + struct drm_display_mode mode; > + > + drm_mode_init(&mode, &phys_enc->cached_mode); > > if (!dpu_encoder_phys_vid_is_master(phys_enc)) > return -EINVAL;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ddd9d89cd456..e7813c6f7bd9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -248,12 +248,13 @@ static void dpu_encoder_phys_vid_setup_timing_engine( unsigned long lock_flags; struct dpu_hw_intf_cfg intf_cfg = { 0 }; + drm_mode_init(&mode, &phys_enc->cached_mode); + if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); return; } - mode = phys_enc->cached_mode; if (!phys_enc->hw_intf->ops.setup_timing_gen) { DPU_ERROR("timing engine setup is not supported\n"); return; @@ -652,7 +653,9 @@ static int dpu_encoder_phys_vid_get_frame_count( { struct intf_status s = {0}; u32 fetch_start = 0; - struct drm_display_mode mode = phys_enc->cached_mode; + struct drm_display_mode mode; + + drm_mode_init(&mode, &phys_enc->cached_mode); if (!dpu_encoder_phys_vid_is_master(phys_enc)) return -EINVAL;