diff mbox series

[v3,3/3] arm64: dts: qcom: sm6115: Add USB SS qmp phy node

Message ID 20221215094532.589291-4-bhupesh.sharma@linaro.org
State Superseded
Headers show
Series arm64: dts: sm6115: Add USB SS qmp phy node and perform some cleanups | expand

Commit Message

Bhupesh Sharma Dec. 15, 2022, 9:45 a.m. UTC 
Add USB superspeed qmp phy node to dtsi.
Make sure that the oneplus board dts (which includes the
sm4250.dtsi) continues to work as intended.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 .../boot/dts/qcom/sm4250-oneplus-billie2.dts  |  3 ++
 arch/arm64/boot/dts/qcom/sm6115.dtsi          | 37 ++++++++++++++++++-
 2 files changed, 38 insertions(+), 2 deletions(-)

Comments

Bjorn Andersson Jan. 6, 2023, 5:46 p.m. UTC | #1 
On Thu, Dec 15, 2022 at 03:15:32PM +0530, Bhupesh Sharma wrote:
> Add USB superspeed qmp phy node to dtsi.
> Make sure that the oneplus board dts (which includes the
> sm4250.dtsi) continues to work as intended.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  .../boot/dts/qcom/sm4250-oneplus-billie2.dts  |  3 ++
>  arch/arm64/boot/dts/qcom/sm6115.dtsi          | 37 ++++++++++++++++++-
>  2 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> index 3f39f25e0721e..4f0d65574448b 100644
> --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> @@ -232,6 +232,9 @@ &usb {
>  &usb_dwc3 {
>  	maximum-speed = "high-speed";
>  	dr_mode = "peripheral";
> +
> +	phys = <&usb_hsphy>;
> +	phy-names = "usb2-phy";
>  };
>  
>  &usb_hsphy {
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index e4ce135264f3d..030763187cc3f 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -579,6 +579,39 @@ usb_hsphy: phy@1613000 {
>  			status = "disabled";
>  		};
>  
> +		usb_qmpphy: phy@1615000 {
> +			compatible = "qcom,sm6115-qmp-usb3-phy";
> +			reg = <0x01615000 0x200>;
> +			clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> +				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> +				 <&gcc GCC_AHB2PHY_USB_CLK>;
> +			clock-names = "com_aux",
> +				      "ref",
> +				      "cfg_ahb";
> +			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
> +				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
> +			reset-names = "phy", "phy_phy";
> +			status = "disabled";
> +			#clock-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			usb_ssphy: phy@1615200 {

These patches looks good, but before introducing any
qcom,sm6115-qmp-usb3-phy in any DT, could we please update the binding
and driver to the new flattened format - to avoid having to revisit this
when we try to introduce DP (which I'm guessing this instance has?)

Regards,
Bjorn

> +				reg = <0x01615200 0x200>,
> +				      <0x01615400 0x200>,
> +				      <0x01615c00 0x400>,
> +				      <0x01615600 0x200>,
> +				      <0x01615800 0x200>,
> +				      <0x01615a00 0x100>;
> +				#phy-cells = <0>;
> +				#clock-cells = <1>;
> +				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> +				clock-names = "pipe0";
> +				clock-output-names = "usb3_phy_pipe_clk_src";
> +			};
> +		};
> +
>  		qfprom@1b40000 {
>  			compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
>  			reg = <0x01b40000 0x7000>;
> @@ -1023,8 +1056,8 @@ usb_dwc3: usb@4e00000 {
>  				compatible = "snps,dwc3";
>  				reg = <0x04e00000 0xcd00>;
>  				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> -				phys = <&usb_hsphy>;
> -				phy-names = "usb2-phy";
> +				phys = <&usb_hsphy>, <&usb_ssphy>;
> +				phy-names = "usb2-phy", "usb3-phy";
>  				iommus = <&apps_smmu 0x120 0x0>;
>  				snps,dis_u2_susphy_quirk;
>  				snps,dis_enblslpm_quirk;
> -- 
> 2.38.1
>
Konrad Dybcio Jan. 7, 2023, 10:24 a.m. UTC | #2 
On 6.01.2023 18:46, Bjorn Andersson wrote:
> On Thu, Dec 15, 2022 at 03:15:32PM +0530, Bhupesh Sharma wrote:
>> Add USB superspeed qmp phy node to dtsi.
>> Make sure that the oneplus board dts (which includes the
>> sm4250.dtsi) continues to work as intended.
>>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
>> ---
>>  .../boot/dts/qcom/sm4250-oneplus-billie2.dts  |  3 ++
>>  arch/arm64/boot/dts/qcom/sm6115.dtsi          | 37 ++++++++++++++++++-
>>  2 files changed, 38 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>> index 3f39f25e0721e..4f0d65574448b 100644
>> --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>> @@ -232,6 +232,9 @@ &usb {
>>  &usb_dwc3 {
>>  	maximum-speed = "high-speed";
>>  	dr_mode = "peripheral";
>> +
>> +	phys = <&usb_hsphy>;
>> +	phy-names = "usb2-phy";
>>  };
>>  
>>  &usb_hsphy {
>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> index e4ce135264f3d..030763187cc3f 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> @@ -579,6 +579,39 @@ usb_hsphy: phy@1613000 {
>>  			status = "disabled";
>>  		};
>>  
>> +		usb_qmpphy: phy@1615000 {
>> +			compatible = "qcom,sm6115-qmp-usb3-phy";
>> +			reg = <0x01615000 0x200>;
>> +			clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
>> +				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
>> +				 <&gcc GCC_AHB2PHY_USB_CLK>;
>> +			clock-names = "com_aux",
>> +				      "ref",
>> +				      "cfg_ahb";
>> +			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
>> +				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
>> +			reset-names = "phy", "phy_phy";
>> +			status = "disabled";
>> +			#clock-cells = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			usb_ssphy: phy@1615200 {
> 
> These patches looks good, but before introducing any
> qcom,sm6115-qmp-usb3-phy in any DT, could we please update the binding
> and driver to the new flattened format - to avoid having to revisit this
> when we try to introduce DP (which I'm guessing this instance has?)
FWIW there's only a single DSI intf (and a single disabled one) on this SoC.

Konrad
> 
> Regards,
> Bjorn
> 
>> +				reg = <0x01615200 0x200>,
>> +				      <0x01615400 0x200>,
>> +				      <0x01615c00 0x400>,
>> +				      <0x01615600 0x200>,
>> +				      <0x01615800 0x200>,
>> +				      <0x01615a00 0x100>;
>> +				#phy-cells = <0>;
>> +				#clock-cells = <1>;
>> +				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> +				clock-names = "pipe0";
>> +				clock-output-names = "usb3_phy_pipe_clk_src";
>> +			};
>> +		};
>> +
>>  		qfprom@1b40000 {
>>  			compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
>>  			reg = <0x01b40000 0x7000>;
>> @@ -1023,8 +1056,8 @@ usb_dwc3: usb@4e00000 {
>>  				compatible = "snps,dwc3";
>>  				reg = <0x04e00000 0xcd00>;
>>  				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>> -				phys = <&usb_hsphy>;
>> -				phy-names = "usb2-phy";
>> +				phys = <&usb_hsphy>, <&usb_ssphy>;
>> +				phy-names = "usb2-phy", "usb3-phy";
>>  				iommus = <&apps_smmu 0x120 0x0>;
>>  				snps,dis_u2_susphy_quirk;
>>  				snps,dis_enblslpm_quirk;
>> -- 
>> 2.38.1
>>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
index 3f39f25e0721e..4f0d65574448b 100644
--- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
+++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
@@ -232,6 +232,9 @@  &usb {
 &usb_dwc3 {
 	maximum-speed = "high-speed";
 	dr_mode = "peripheral";
+
+	phys = <&usb_hsphy>;
+	phy-names = "usb2-phy";
 };
 
 &usb_hsphy {
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index e4ce135264f3d..030763187cc3f 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -579,6 +579,39 @@  usb_hsphy: phy@1613000 {
 			status = "disabled";
 		};
 
+		usb_qmpphy: phy@1615000 {
+			compatible = "qcom,sm6115-qmp-usb3-phy";
+			reg = <0x01615000 0x200>;
+			clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+				 <&gcc GCC_AHB2PHY_USB_CLK>;
+			clock-names = "com_aux",
+				      "ref",
+				      "cfg_ahb";
+			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
+			reset-names = "phy", "phy_phy";
+			status = "disabled";
+			#clock-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usb_ssphy: phy@1615200 {
+				reg = <0x01615200 0x200>,
+				      <0x01615400 0x200>,
+				      <0x01615c00 0x400>,
+				      <0x01615600 0x200>,
+				      <0x01615800 0x200>,
+				      <0x01615a00 0x100>;
+				#phy-cells = <0>;
+				#clock-cells = <1>;
+				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "usb3_phy_pipe_clk_src";
+			};
+		};
+
 		qfprom@1b40000 {
 			compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
 			reg = <0x01b40000 0x7000>;
@@ -1023,8 +1056,8 @@  usb_dwc3: usb@4e00000 {
 				compatible = "snps,dwc3";
 				reg = <0x04e00000 0xcd00>;
 				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb_hsphy>;
-				phy-names = "usb2-phy";
+				phys = <&usb_hsphy>, <&usb_ssphy>;
+				phy-names = "usb2-phy", "usb3-phy";
 				iommus = <&apps_smmu 0x120 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;