| Message ID | 20221213-sm6350-cci-v2-0-15c2c14c34bb@fairphone.com |
|---|---|
| Headers | show |
| Series | Add CCI bus support for SM6350 | expand |
On 20.01.2023 14:13, Luca Weiss wrote: > Add nodes for the two CCI blocks found on SM6350. > > The first contains two i2c busses and while the second one might also > contains two busses, the downstream kernel only has one configured, and > some boards use the GPIOs for the potential cci1_i2c1 one other > purposes, so leave that one unconfigured. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++ > 1 file changed, 132 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 300ced5cda57..802d7f494162 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/qcom,gcc-sm6350.h> > #include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sm6350-camcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interconnect/qcom,icc.h> > @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { > }; > }; > > + cci0: cci@ac4a000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac4a000 0 0x1000>; > + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_0_CLK>, > + <&camcc CAMCC_CCI_0_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_0_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-1 = <&cci0_sleep &cci1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac4b000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac4b000 0 0x1000>; > + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_1_CLK>, > + <&camcc CAMCC_CCI_1_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_1_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-0 = <&cci2_default>; > + pinctrl-1 = <&cci2_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ > + }; > + > camcc: clock-controller@ad00000 { > compatible = "qcom,sm6350-camcc"; > reg = <0 0x0ad00000 0 0x16000>; > @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { > #interrupt-cells = <2>; > gpio-ranges = <&tlmm 0 0 157>; > > + cci0_default: cci0-default-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci0_sleep: cci0-sleep-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci1_default: cci1-default-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci1_sleep: cci1-sleep-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci2_default: cci2-default-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci2_sleep: cci2-sleep-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > sdc2_off_state: sdc2-off-state { > clk-pins { > pins = "sdc2_clk"; >
On Fri, 20 Jan 2023 14:13:43 +0100, Luca Weiss wrote: > Add the camera clock controller node and CCI nodes to sm6350 dtsi and enable > the i2c busses on Fairphone 4 dts. > > This is tested using PM8008 regulator patches from the lists which power the > cameras, and using i2cdetect/i2cget/i2cset reading the sensor ID registers. > > > [...] Applied, thanks! [2/4] arm64: dts: qcom: sm6350: Add camera clock controller commit: 4ab96c9c4012770f50f90bda2e61ef774bb63be5 [3/4] arm64: dts: qcom: sm6350: Add CCI nodes commit: 033fb15f39b8f092bf4664144784a3e19c834f26 [4/4] arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI busses commit: bd3dc67bbc34d684c7d94865bb10283508d7cd84 Best regards,
Add the camera clock controller node and CCI nodes to sm6350 dtsi and enable the i2c busses on Fairphone 4 dts. This is tested using PM8008 regulator patches from the lists which power the cameras, and using i2cdetect/i2cget/i2cset reading the sensor ID registers. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- Changes in v2: - Correct ordering of attributes in sm6350.dtsi (#*-cells, pinctrl-names, bias-*) - Link to v1: https://lore.kernel.org/r/20221213-sm6350-cci-v1-0-e5d0c36e0c4f@fairphone.com --- Luca Weiss (4): dt-bindings: i2c: qcom-cci: Document SM6350 compatible arm64: dts: qcom: sm6350: Add camera clock controller arm64: dts: qcom: sm6350: Add CCI nodes arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI busses .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 141 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 20 +++ 3 files changed, 163 insertions(+) --- base-commit: 1578f85d549045aac441821064e7953732460e51 change-id: 20221213-sm6350-cci-38baf19ace3b Best regards,