| Message ID | 20230215070400.5901-1-manivannan.sadhasivam@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: dts: qcom: Supply clock from cpufreq node to CPUs | expand |
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Hi, > > As a follow-up of [1], this series adds support for supplying clock from > cpufreq node to CPUs for rest of the SoCs. > > This series has been tested on SDM845, SM8450 and SC8280XP based boards. > > Thanks, > Mani > > [1] https://lore.kernel.org/linux-arm-msm/20221117053145.10409-1-manivannan.sadhasivam@linaro.org/ Maybe it would be beneficial to mark '#clock-cells' required in bindings now, to prevent people from hitting that OPP bug? Konrad > > Manivannan Sadhasivam (12): > arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs > arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 5 +++++ > arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++++++ > arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ > 12 files changed, 104 insertions(+) >
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks > to the CPU cores. But this relationship is not represented in DTS so far. > > So let's make cpufreq node as the clock provider and CPU nodes as the > consumers. The clock index for each CPU node is based on the frequency > domain index. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 9910006c32aa..21b4f668889d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -68,6 +68,7 @@ CPU0: cpu@0 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > power-domains = <&CPU_PD0>; > @@ -91,6 +92,7 @@ CPU1: cpu@100 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_100>; > power-domains = <&CPU_PD1>; > @@ -110,6 +112,7 @@ CPU2: cpu@200 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_200>; > power-domains = <&CPU_PD2>; > @@ -129,6 +132,7 @@ CPU3: cpu@300 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x300>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_300>; > power-domains = <&CPU_PD3>; > @@ -148,6 +152,7 @@ CPU4: cpu@400 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x400>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_400>; > power-domains = <&CPU_PD4>; > @@ -167,6 +172,7 @@ CPU5: cpu@500 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x500>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_500>; > power-domains = <&CPU_PD5>; > @@ -186,6 +192,7 @@ CPU6: cpu@600 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x600>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_600>; > power-domains = <&CPU_PD6>; > @@ -205,6 +212,7 @@ CPU7: cpu@700 { > device_type = "cpu"; > compatible = "qcom,kryo"; > reg = <0 0x700>; > + clocks = <&cpufreq_hw 2>; > enable-method = "psci"; > next-level-cache = <&L2_700>; > power-domains = <&CPU_PD7>; > @@ -3341,6 +3349,7 @@ cpufreq_hw: cpufreq@17d91000 { > <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; > #freq-domain-cells = <1>; > + #clock-cells = <1>; > }; > > pmu@24091000 {
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks > to the CPU cores. But this relationship is not represented in DTS so far. > > So let's make cpufreq node as the clock provider and CPU nodes as the > consumers. The clock index for each CPU node is based on the frequency > domain index. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index ebfa21e9ed8a..53f0076f20f6 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -76,6 +76,7 @@ CPU0: cpu@0 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -103,6 +104,7 @@ CPU1: cpu@100 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -126,6 +128,7 @@ CPU2: cpu@200 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -149,6 +152,7 @@ CPU3: cpu@300 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -172,6 +176,7 @@ CPU4: cpu@400 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x400>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -195,6 +200,7 @@ CPU5: cpu@500 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x500>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > cpu-idle-states = <&LITTLE_CPU_SLEEP_0 > &LITTLE_CPU_SLEEP_1 > @@ -218,6 +224,7 @@ CPU6: cpu@600 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x600>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > cpu-idle-states = <&BIG_CPU_SLEEP_0 > &BIG_CPU_SLEEP_1 > @@ -241,6 +248,7 @@ CPU7: cpu@700 { > device_type = "cpu"; > compatible = "qcom,kryo468"; > reg = <0x0 0x700>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > cpu-idle-states = <&BIG_CPU_SLEEP_0 > &BIG_CPU_SLEEP_1 > @@ -3578,6 +3586,7 @@ cpufreq_hw: cpufreq@18323000 { > clock-names = "xo", "alternate"; > > #freq-domain-cells = <1>; > + #clock-cells = <1>; > }; > > wifi: wifi@18800000 {
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks > to the CPU cores. But this relationship is not represented in DTS so far. > > So let's make cpufreq node as the clock provider and CPU nodes as the > consumers. The clock index for each CPU node is based on the frequency > domain index. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 0a422637b61f..1b423c42ec0d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -48,6 +48,7 @@ CPU0: cpu@0 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -69,6 +70,7 @@ CPU1: cpu@100 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_100>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -86,6 +88,7 @@ CPU2: cpu@200 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_200>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -103,6 +106,7 @@ CPU3: cpu@300 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_300>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -120,6 +124,7 @@ CPU4: cpu@400 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x400>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_400>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -137,6 +142,7 @@ CPU5: cpu@500 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x500>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_500>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -155,6 +161,7 @@ CPU6: cpu@600 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x600>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_600>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -172,6 +179,7 @@ CPU7: cpu@700 { > device_type = "cpu"; > compatible = "qcom,kryo685"; > reg = <0x0 0x700>; > + clocks = <&cpufreq_hw 2>; > enable-method = "psci"; > next-level-cache = <&L2_700>; > qcom,freq-domain = <&cpufreq_hw 2>; > @@ -2283,6 +2291,7 @@ cpufreq_hw: cpufreq@18591000 { > clock-names = "xo", "alternate"; > > #freq-domain-cells = <1>; > + #clock-cells = <1>; > }; > > ufs_mem_hc: ufshc@1d84000 {
On 15.02.2023 08:03, Manivannan Sadhasivam wrote: > Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks > to the CPU cores. But this relationship is not represented in DTS so far. > > So let's make cpufreq node as the clock provider and CPU nodes as the > consumers. The clock index for each CPU node is based on the frequency > domain index. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi > index 31b88c738510..58d3b4785401 100644 > --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi > @@ -39,6 +39,7 @@ CPU0: cpu@0 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -58,6 +59,7 @@ CPU1: cpu@100 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_100>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -74,6 +76,7 @@ CPU2: cpu@200 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_200>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -90,6 +93,7 @@ CPU3: cpu@300 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_300>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -106,6 +110,7 @@ CPU4: cpu@400 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x400>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_400>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -122,6 +127,7 @@ CPU5: cpu@500 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x500>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > next-level-cache = <&L2_500>; > qcom,freq-domain = <&cpufreq_hw 0>; > @@ -139,6 +145,7 @@ CPU6: cpu@600 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x600>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_600>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -155,6 +162,7 @@ CPU7: cpu@700 { > device_type = "cpu"; > compatible = "qcom,kryo660"; > reg = <0x0 0x700>; > + clocks = <&cpufreq_hw 1>; > enable-method = "psci"; > next-level-cache = <&L2_700>; > qcom,freq-domain = <&cpufreq_hw 1>; > @@ -1383,6 +1391,7 @@ cpufreq_hw: cpufreq@fd91000 { > <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; > #freq-domain-cells = <1>; > + #clock-cells = <1>; > }; > }; >
On Wed, 15 Feb 2023 12:33:48 +0530, Manivannan Sadhasivam wrote: > As a follow-up of [1], this series adds support for supplying clock from > cpufreq node to CPUs for rest of the SoCs. > > This series has been tested on SDM845, SM8450 and SC8280XP based boards. > > Thanks, > Mani > > [...] Applied, thanks! [01/12] arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs commit: 2af2ef08c0ba052aefca20609572d67e0633b1ef [02/12] arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs commit: 667d8a2039608c4c848179cb45282204eadeb157 [03/12] arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs commit: afa34380d973491e87ab01d13c387528e2e1c476 [04/12] arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs commit: 1b0911fe3edb0895c43db4c19729b3c300028189 [05/12] arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs commit: d78cb07dbc1d384a8665b08918d188ee670ec45b [06/12] arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs commit: fcca74d893f3511a1e95869b1b3db3abb69bfb3b [07/12] arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs commit: 7b39c98ff7e80f7e2bdf3c73829480e6ac123fb5 [08/12] arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs commit: fc7258948c4a9e5dd2670adfcc80b13c621fbcd1 [09/12] arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs commit: c2a18730f0aaa2088a259f123e5fedf05f8a7041 [10/12] arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs commit: 2051f735b37d8e49f84914df11eb7b4a3a16349f [11/12] arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs commit: d9ab57eec39db8bf72951e00cde5ab117bcad6d8 [12/12] arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs commit: 0e6538e2d973bdfdf4d65a7d4b8baf1b7cdf75f0 Best regards,