| Message ID | 20230405072836.1690248-9-bhupesh.sharma@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: Enable Crypto Engine for a few Qualcomm SoCs | expand |
On 5.04.2023 09:28, Bhupesh Sharma wrote: > Add crypto engine (CE) and CE BAM related nodes and definitions to > 'sm8150.dtsi'. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 9491be4a6bf0..c104d0b12dc6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -2081,6 +2081,28 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0 0x01dc4000 0 0x24000>; > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + iommus = <&apps_smmu 0x514 0x0011>, > + <&apps_smmu 0x516 0x0011>; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8150-qce", "qcom,qce"; > + reg = <0 0x01dfa000 0 0x6000>; > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + iommus = <&apps_smmu 0x514 0x0011>, > + <&apps_smmu 0x516 0x0011>; Downstream uses these (sid, mask) combos: qcedev: 0x0506 0x0011 0x0516 0x0011 // equal to 0x506 0x11 qcom_cedev_ns_cb: 0x512 0 0x518 0 0x519 0 0x51f 0 Shouldn't we use them too? Konrad > + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; > + interconnect-names = "memory"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>;
Hi Konrad, Sorry for the late reply, but I wanted to look at the latest downstream code before responding. On Thu, 6 Apr 2023 at 19:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > On 5.04.2023 09:28, Bhupesh Sharma wrote: > > Add crypto engine (CE) and CE BAM related nodes and definitions to > > 'sm8150.dtsi'. > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > index 9491be4a6bf0..c104d0b12dc6 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > @@ -2081,6 +2081,28 @@ ufs_mem_phy_lanes: phy@1d87400 { > > }; > > }; > > > > + cryptobam: dma-controller@1dc4000 { > > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > > + reg = <0 0x01dc4000 0 0x24000>; > > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + qcom,ee = <0>; > > + qcom,controlled-remotely; > > + iommus = <&apps_smmu 0x514 0x0011>, > > + <&apps_smmu 0x516 0x0011>; > > + }; > > + > > + crypto: crypto@1dfa000 { > > + compatible = "qcom,sm8150-qce", "qcom,qce"; > > + reg = <0 0x01dfa000 0 0x6000>; > > + dmas = <&cryptobam 4>, <&cryptobam 5>; > > + dma-names = "rx", "tx"; > > + iommus = <&apps_smmu 0x514 0x0011>, > > + <&apps_smmu 0x516 0x0011>; > Downstream uses these (sid, mask) combos: > > qcedev: > 0x0506 0x0011 > 0x0516 0x0011 // equal to 0x506 0x11 > > qcom_cedev_ns_cb: > 0x512 0 > 0x518 0 > 0x519 0 > 0x51f 0 > > Shouldn't we use them too? Sure, but the following are the latest values used in the downstream .dtsi, so I used them in the latest version and tested with the same on sa8115p-adp and sm8150-mtp without any issues: qcedev: 0x0502 0x0641 0x0504 0x0011 qcom_cedev_ns_cb: 0x0506 0x0011 0x0508 0x0011 0x0512 0x0000 I dropped: 0x0514 0x0011 // equal to 0x504 0x11 0x0516 0x0011 // equal to 0x506 0x11 0x0518 0x0011 // equal to 0x508 0x11 Thanks for pointing this out. Regards, Bhupesh
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 9491be4a6bf0..c104d0b12dc6 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2081,6 +2081,28 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x514 0x0011>, + <&apps_smmu 0x516 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x514 0x0011>, + <&apps_smmu 0x516 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8150.dtsi'. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)