| Message ID | 20230704064610.292603-4-xingyu.wu@starfivetech.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Tue, Jul 04, 2023 at 02:46:06PM +0800, Xingyu Wu wrote: > Add PLL clock inputs from PLL clock generator. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> As expected this produces warnings for the existing, in-tree, devicetrees which go away when the later dts patches are applied. It'd be good to mention that its intentional if you end up sending another version of the series. Otherwise, this looks good to me too. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > --- > .../bindings/clock/starfive,jh7110-syscrg.yaml | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > index 84373ae31644..5ba0a885aa80 100644 > --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > @@ -27,6 +27,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > - items: > - description: Main Oscillator (24 MHz) > @@ -38,6 +41,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > clock-names: > oneOf: > @@ -52,6 +58,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > - items: > - const: osc > @@ -63,6 +72,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > '#clock-cells': > const: 1 > @@ -93,12 +105,14 @@ examples: > <&gmac1_rgmii_rxin>, > <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > - <&tdm_ext>, <&mclk_ext>; > + <&tdm_ext>, <&mclk_ext>, > + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; > clock-names = "osc", "gmac1_rmii_refin", > "gmac1_rgmii_rxin", > "i2stx_bclk_ext", "i2stx_lrck_ext", > "i2srx_bclk_ext", "i2srx_lrck_ext", > - "tdm_ext", "mclk_ext"; > + "tdm_ext", "mclk_ext", > + "pll0_out", "pll1_out", "pll2_out"; > #clock-cells = <1>; > #reset-cells = <1>; > }; > -- > 2.25.1 >
On 2023/7/5 6:23, Conor Dooley wrote: > On Tue, Jul 04, 2023 at 02:46:06PM +0800, Xingyu Wu wrote: >> Add PLL clock inputs from PLL clock generator. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > > As expected this produces warnings for the existing, in-tree, > devicetrees which go away when the later dts patches are applied. > It'd be good to mention that its intentional if you end up sending > another version of the series. > > Otherwise, this looks good to me too. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Thanks, I will add the mentions in next version. Best regards, Xingyu Wu
On Tue, 4 Jul 2023 at 08:49, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > Add PLL clock inputs from PLL clock generator. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > .../bindings/clock/starfive,jh7110-syscrg.yaml | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > index 84373ae31644..5ba0a885aa80 100644 > --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > @@ -27,6 +27,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > - items: > - description: Main Oscillator (24 MHz) > @@ -38,6 +41,9 @@ properties: > - description: External I2S RX left/right channel clock > - description: External TDM clock > - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 > > clock-names: > oneOf: > @@ -52,6 +58,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > - items: > - const: osc > @@ -63,6 +72,9 @@ properties: > - const: i2srx_lrck_ext > - const: tdm_ext > - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out > > '#clock-cells': > const: 1 > @@ -93,12 +105,14 @@ examples: > <&gmac1_rgmii_rxin>, > <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > - <&tdm_ext>, <&mclk_ext>; > + <&tdm_ext>, <&mclk_ext>, > + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; > clock-names = "osc", "gmac1_rmii_refin", > "gmac1_rgmii_rxin", > "i2stx_bclk_ext", "i2stx_lrck_ext", > "i2srx_bclk_ext", "i2srx_lrck_ext", > - "tdm_ext", "mclk_ext"; > + "tdm_ext", "mclk_ext", > + "pll0_out", "pll1_out", "pll2_out"; > #clock-cells = <1>; > #reset-cells = <1>; > }; > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml index 84373ae31644..5ba0a885aa80 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -27,6 +27,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 - items: - description: Main Oscillator (24 MHz) @@ -38,6 +41,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 clock-names: oneOf: @@ -52,6 +58,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out - items: - const: osc @@ -63,6 +72,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out '#clock-cells': const: 1 @@ -93,12 +105,14 @@ examples: <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; };
Add PLL clock inputs from PLL clock generator. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../bindings/clock/starfive,jh7110-syscrg.yaml | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)