| Message ID | 20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com |
|---|---|
| Headers | show |
| Series | spi: qup: Allow scaling power domains and interconnect | expand |
On 12.09.2023 16:30, Stephan Gerhold wrote: > Parse the OPP table from the device tree and use dev_pm_opp_set_rate() > instead of clk_set_rate() to allow making performance state for power > domains specified in the OPP table. > > This is needed to guarantee correct behavior of the clock, especially > with the higher clock/SPI bus frequencies. > > Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> > --- Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
Make it possible to scale performance states of the power domain and interconnect of the SPI QUP controller in relation to the selected SPI speed / core clock. This is done separately by: - Parsing the OPP table from the device tree for performance state votes of the power domain - Voting for the necessary bandwidth on the interconnect path to DRAM Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> --- Stephan Gerhold (4): spi: dt-bindings: qup: Document power-domains and OPP spi: qup: Parse OPP table for DVFS support spi: dt-bindings: qup: Document interconnects spi: qup: Vote for interconnect bandwidth to DRAM .../devicetree/bindings/spi/qcom,spi-qup.yaml | 13 ++++++ drivers/spi/spi-qup.c | 50 +++++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) --- base-commit: 678466ba68915d452c200b78d0385931e6f8e907 change-id: 20230912-spi-qup-dvfs-71fc8a5e0cb1 Best regards,