| Message ID | 1698202408-14608-8-git-send-email-quic_taozha@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/8] dt-bindings: arm: Add support for CMB element size | expand |
On Wed, Oct 25, 2023 at 10:53:27AM +0800, Tao Zhang wrote: > Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) > for TPDM. It specifies the number of CMB MSR registers supported by > the TDPM. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index f9a2025..a586b80a 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -69,6 +69,15 @@ properties: > minimum: 0 > maximum: 32 > > + qcom,cmb-msrs-num: > + description: > + Specifies the number of CMB MSR(mux select register) registers supported > + by the monitor. If this property is not configured or set to 0, it means > + this TPDM doesn't support CMB MSR. > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 32 default: 0 > + > clocks: > maxItems: 1 > > @@ -124,6 +133,7 @@ examples: > reg-names = "tpdm-base"; > > qcom,cmb-element-size = /bits/ 8 <64>; > + qcom,cmb-msrs-num = <32>; > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > -- > 2.7.4 >
On 10/27/2023 5:27 AM, Rob Herring wrote: > On Wed, Oct 25, 2023 at 10:53:27AM +0800, Tao Zhang wrote: >> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) >> for TPDM. It specifies the number of CMB MSR registers supported by >> the TDPM. >> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index f9a2025..a586b80a 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -69,6 +69,15 @@ properties: >> minimum: 0 >> maximum: 32 >> >> + qcom,cmb-msrs-num: >> + description: >> + Specifies the number of CMB MSR(mux select register) registers supported >> + by the monitor. If this property is not configured or set to 0, it means >> + this TPDM doesn't support CMB MSR. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 0 >> + maximum: 32 > default: 0 If the TPDM doesn't support CMB MSR, we will not configure this property. Set to 0 to indicate that CMB MSR is not supported and is only an optional method. Is it necessary to add this "default" value here? Best, Tao >> + >> clocks: >> maxItems: 1 >> >> @@ -124,6 +133,7 @@ examples: >> reg-names = "tpdm-base"; >> >> qcom,cmb-element-size = /bits/ 8 <64>; >> + qcom,cmb-msrs-num = <32>; >> >> clocks = <&aoss_qmp>; >> clock-names = "apb_pclk"; >> -- >> 2.7.4 >>
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index f9a2025..a586b80a 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -69,6 +69,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msrs-num: + description: + Specifies the number of CMB MSR(mux select register) registers supported + by the monitor. If this property is not configured or set to 0, it means + this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -124,6 +133,7 @@ examples: reg-names = "tpdm-base"; qcom,cmb-element-size = /bits/ 8 <64>; + qcom,cmb-msrs-num = <32>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";