| Message ID | 20240123224842.18485-6-philmd@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/arm/aspeed: Check for CPU types in machine_run_board_init() | expand |
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote: > Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). > Convert it to a NULL-terminated array (of a single non-NULL element). > > Set MachineClass::valid_cpu_types[] to use the common machine code > to provide hints when the requested CPU is invalid (see commit > e702cbc19e ("machine: Improve is_cpu_type_supported()"). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > include/hw/arm/aspeed_soc.h | 3 ++- > hw/arm/aspeed.c | 1 + > hw/arm/aspeed_ast10x0.c | 6 +++++- > hw/arm/aspeed_ast2400.c | 12 ++++++++++-- > hw/arm/aspeed_ast2600.c | 6 +++++- > hw/arm/aspeed_soc_common.c | 5 ++++- > 6 files changed, 27 insertions(+), 6 deletions(-) > > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index a060a59918..0db5a41e71 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -128,7 +128,8 @@ struct AspeedSoCClass { > DeviceClass parent_class; > > const char *name; > - const char *cpu_type; > + /** valid_cpu_types: NULL terminated array of a single CPU type. */ > + const char * const *valid_cpu_types; > uint32_t silicon_rev; > uint64_t sram_size; > uint64_t secsram_size; > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 636a6269aa..1be3b6bcae 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) > mc->default_cpus = mc->min_cpus > = mc->max_cpus > = sc->num_cpus; > + mc->valid_cpu_types = sc->valid_cpu_types; > } > > static void aspeed_machine_class_init(ObjectClass *oc, void *data) > diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c > index dca601a3f9..c3b5116a6a 100644 > --- a/hw/arm/aspeed_ast10x0.c > +++ b/hw/arm/aspeed_ast10x0.c > @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) > > static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ > + NULL > + }; > DeviceClass *dc = DEVICE_CLASS(klass); > AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); > > dc->realize = aspeed_soc_ast1030_realize; > > sc->name = "ast1030-a1"; > - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ > + sc->valid_cpu_types = valid_cpu_types; > sc->silicon_rev = AST1030_A1_SILICON_REV; > sc->sram_size = 0xc0000; > sc->secsram_size = 0x40000; /* 256 * KiB */ > diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c > index 3baf95916d..8829561bb6 100644 > --- a/hw/arm/aspeed_ast2400.c > +++ b/hw/arm/aspeed_ast2400.c > @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) > > static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("arm926"), > + NULL > + }; > AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); > DeviceClass *dc = DEVICE_CLASS(oc); > > @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) > dc->user_creatable = false; > > sc->name = "ast2400-a1"; > - sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); > + sc->valid_cpu_types = valid_cpu_types; > sc->silicon_rev = AST2400_A1_SILICON_REV; > sc->sram_size = 0x8000; > sc->spis_num = 1; > @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) > > static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("arm1176"), > + NULL > + }; > AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); > DeviceClass *dc = DEVICE_CLASS(oc); > > @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) > dc->user_creatable = false; > > sc->name = "ast2500-a1"; > - sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); > + sc->valid_cpu_types = valid_cpu_types; > sc->silicon_rev = AST2500_A1_SILICON_REV; > sc->sram_size = 0x9000; > sc->spis_num = 2; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index b264433cf0..46baba0e41 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) > > static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-a7"), > + NULL > + }; > DeviceClass *dc = DEVICE_CLASS(oc); > AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); > > dc->realize = aspeed_soc_ast2600_realize; > > sc->name = "ast2600-a3"; > - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); > + sc->valid_cpu_types = valid_cpu_types; > sc->silicon_rev = AST2600_A3_SILICON_REV; > sc->sram_size = 0x16400; > sc->spis_num = 2; > diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c > index 36ca189ce9..123a0c432c 100644 > --- a/hw/arm/aspeed_soc_common.c > +++ b/hw/arm/aspeed_soc_common.c > @@ -20,7 +20,10 @@ > > const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) > { > - return sc->cpu_type; > + assert(sc->valid_cpu_types); > + assert(sc->valid_cpu_types[0]); > + assert(!sc->valid_cpu_types[1]); > + return sc->valid_cpu_types[0]; > } > > qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote: > Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). > Convert it to a NULL-terminated array (of a single non-NULL element). > > Set MachineClass::valid_cpu_types[] to use the common machine code > to provide hints when the requested CPU is invalid (see commit > e702cbc19e ("machine: Improve is_cpu_type_supported()"). > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > include/hw/arm/aspeed_soc.h | 3 ++- > hw/arm/aspeed.c | 1 + > hw/arm/aspeed_ast10x0.c | 6 +++++- > hw/arm/aspeed_ast2400.c | 12 ++++++++++-- > hw/arm/aspeed_ast2600.c | 6 +++++- > hw/arm/aspeed_soc_common.c | 5 ++++- > 6 files changed, 27 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote: > Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). > Convert it to a NULL-terminated array (of a single non-NULL element). > > Set MachineClass::valid_cpu_types[] to use the common machine code > to provide hints when the requested CPU is invalid (see commit > e702cbc19e ("machine: Improve is_cpu_type_supported()"). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/hw/arm/aspeed_soc.h | 3 ++- > hw/arm/aspeed.c | 1 + > hw/arm/aspeed_ast10x0.c | 6 +++++- > hw/arm/aspeed_ast2400.c | 12 ++++++++++-- > hw/arm/aspeed_ast2600.c | 6 +++++- > hw/arm/aspeed_soc_common.c | 5 ++++- > 6 files changed, 27 insertions(+), 6 deletions(-) > Reviewed-by: Gavin Shan <gshan@redhat.com>
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a59918..0db5a41e71 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 636a6269aa..1be3b6bcae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; + mc->valid_cpu_types = sc->valid_cpu_types; } static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9..c3b5116a6a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc = DEVICE_CLASS(klass); AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); dc->realize = aspeed_soc_ast1030_realize; sc->name = "ast1030-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST1030_A1_SILICON_REV; sc->sram_size = 0xc0000; sc->secsram_size = 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 3baf95916d..8829561bb6 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; sc->name = "ast2400-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2400_A1_SILICON_REV; sc->sram_size = 0x8000; sc->spis_num = 1; @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; sc->name = "ast2500-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2500_A1_SILICON_REV; sc->sram_size = 0x9000; sc->spis_num = 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b264433cf0..46baba0e41 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc = DEVICE_CLASS(oc); AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); dc->realize = aspeed_soc_ast2600_realize; sc->name = "ast2600-a3"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2600_A3_SILICON_REV; sc->sram_size = 0x16400; sc->spis_num = 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce9..123a0c432c 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-)