| Message ID | 20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com |
|---|---|
| Headers | show |
| Series | Add initial support for QCS8300 | expand |
On Wed, Sep 04, 2024 at 04:33:44PM GMT, Jingyi Wang wrote: > From: Xin Liu <quic_liuxin@quicinc.com> > > Document the QMP UFS PHY compatible for QCS8300 to support physical > layer functionality for USB found on the SoC. So this is talking about USB, but the patch changes UFS. Please adjust. > > Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> > Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> > --- > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > index f9cfbd0b2de6..a3540f7a8ef8 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > @@ -18,6 +18,7 @@ properties: > enum: > - qcom,msm8996-qmp-ufs-phy > - qcom,msm8998-qmp-ufs-phy > + - qcom,qcs8300-qmp-ufs-phy > - qcom,sa8775p-qmp-ufs-phy > - qcom,sc7180-qmp-ufs-phy > - qcom,sc7280-qmp-ufs-phy > @@ -85,6 +86,7 @@ allOf: > contains: > enum: > - qcom,msm8998-qmp-ufs-phy > + - qcom,qcs8300-qmp-ufs-phy > - qcom,sa8775p-qmp-ufs-phy > - qcom,sc7180-qmp-ufs-phy > - qcom,sc7280-qmp-ufs-phy > > -- > 2.25.1 >
On 9/4/2024 5:36 PM, Krzysztof Kozlowski wrote: > On 04/09/2024 10:33, Jingyi Wang wrote: >> From: Xin Liu <quic_liuxin@quicinc.com> >> >> Add QMP PHY support for QCS8300 which is compatible with SA8775P. >> >> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> index d964bdfe8700..8bad68400736 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> @@ -2010,6 +2010,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { >> }, { >> .compatible = "qcom,msm8998-qmp-ufs-phy", >> .data = &sdm845_ufsphy_cfg, >> + }, { >> + .compatible = "qcom,qcs8300-qmp-ufs-phy", >> + .data = &sa8775p_ufsphy_cfg, > > Is compatible? Then this is redundant. Drop. > > Best regards, > Krzysztof > Will drop that. Thanks, Jingyi
On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote: > On 04/09/2024 10:33, Jingyi Wang wrote: >> Enable clock controller, interrconnect and pinctrl for QCS8300. > > NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig > for entire kernel, not your Qualcomm one. > Will describe it in more detail. >> It needs to be built-in for UART to provide a console. >> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >> --- >> arch/arm64/configs/defconfig | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index 81ca46e3ab4b..a9ba6b25a0ed 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -606,6 +606,7 @@ CONFIG_PINCTRL_MSM8996=y >> CONFIG_PINCTRL_MSM8998=y >> CONFIG_PINCTRL_QCM2290=y >> CONFIG_PINCTRL_QCS404=y >> +CONFIG_PINCTRL_QCS8300=y >> CONFIG_PINCTRL_QDF2XXX=y >> CONFIG_PINCTRL_QDU1000=y >> CONFIG_PINCTRL_SA8775P=y >> @@ -1317,6 +1318,7 @@ CONFIG_MSM_MMCC_8998=m >> CONFIG_QCM_GCC_2290=y >> CONFIG_QCM_DISPCC_2290=m >> CONFIG_QCS_GCC_404=y >> +CONFIG_QCS_GCC_8300=y >> CONFIG_QDU_GCC_1000=y >> CONFIG_SC_CAMCC_8280XP=m >> CONFIG_SC_DISPCC_7280=m >> @@ -1618,6 +1620,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >> CONFIG_INTERCONNECT_QCOM_QCM2290=y >> CONFIG_INTERCONNECT_QCOM_QCS404=m >> +CONFIG_INTERCONNECT_QCOM_QCS8300=y > > Why this cannot be a module? > > I think the commit-msg "It needs to be built-in for UART to provide a console." can explain that, could you please help to share your insights on that? > > Best regards, > Krzysztof > Thanks, Jingyi
On Thu, Sep 05, 2024 at 12:54:35PM GMT, Jingyi Wang wrote: > > > On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote: > > On 04/09/2024 10:33, Jingyi Wang wrote: > >> Enable clock controller, interrconnect and pinctrl for QCS8300. > > > > NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig > > for entire kernel, not your Qualcomm one. > > > Will describe it in more detail. > >> It needs to be built-in for UART to provide a console. > >> > >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> > >> --- > >> arch/arm64/configs/defconfig | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > >> index 81ca46e3ab4b..a9ba6b25a0ed 100644 > >> --- a/arch/arm64/configs/defconfig > >> +++ b/arch/arm64/configs/defconfig > >> @@ -606,6 +606,7 @@ CONFIG_PINCTRL_MSM8996=y > >> CONFIG_PINCTRL_MSM8998=y > >> CONFIG_PINCTRL_QCM2290=y > >> CONFIG_PINCTRL_QCS404=y > >> +CONFIG_PINCTRL_QCS8300=y > >> CONFIG_PINCTRL_QDF2XXX=y > >> CONFIG_PINCTRL_QDU1000=y > >> CONFIG_PINCTRL_SA8775P=y > >> @@ -1317,6 +1318,7 @@ CONFIG_MSM_MMCC_8998=m > >> CONFIG_QCM_GCC_2290=y > >> CONFIG_QCM_DISPCC_2290=m > >> CONFIG_QCS_GCC_404=y > >> +CONFIG_QCS_GCC_8300=y > >> CONFIG_QDU_GCC_1000=y > >> CONFIG_SC_CAMCC_8280XP=m > >> CONFIG_SC_DISPCC_7280=m > >> @@ -1618,6 +1620,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y > >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m > >> CONFIG_INTERCONNECT_QCOM_QCM2290=y > >> CONFIG_INTERCONNECT_QCOM_QCS404=m > >> +CONFIG_INTERCONNECT_QCOM_QCS8300=y > > > > Why this cannot be a module? > > > > > I think the commit-msg "It needs to be built-in for UART to provide a console." can > explain that, could you please help to share your insights on that? Unless loading these modules from initramfs doesn't work, please use =m. The drivers that are enabled here are going to be enabled for everybody using arm64 defconfig, taking up memory on their platforms, etc.
Hi Dmitry, On 9/6/2024 11:18 AM, Dmitry Baryshkov wrote: > On Thu, Sep 05, 2024 at 12:54:35PM GMT, Jingyi Wang wrote: >> >> >> On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote: >>> On 04/09/2024 10:33, Jingyi Wang wrote: >>>> Enable clock controller, interrconnect and pinctrl for QCS8300. >>> >>> NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig >>> for entire kernel, not your Qualcomm one. >>> >> Will describe it in more detail. >>>> It needs to be built-in for UART to provide a console. >>>> >>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> >>>> --- >>>> arch/arm64/configs/defconfig | 3 +++ >>>> 1 file changed, 3 insertions(+) >>>> >>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >>>> index 81ca46e3ab4b..a9ba6b25a0ed 100644 >>>> --- a/arch/arm64/configs/defconfig >>>> +++ b/arch/arm64/configs/defconfig >>>> @@ -606,6 +606,7 @@ CONFIG_PINCTRL_MSM8996=y >>>> CONFIG_PINCTRL_MSM8998=y >>>> CONFIG_PINCTRL_QCM2290=y >>>> CONFIG_PINCTRL_QCS404=y >>>> +CONFIG_PINCTRL_QCS8300=y >>>> CONFIG_PINCTRL_QDF2XXX=y >>>> CONFIG_PINCTRL_QDU1000=y >>>> CONFIG_PINCTRL_SA8775P=y >>>> @@ -1317,6 +1318,7 @@ CONFIG_MSM_MMCC_8998=m >>>> CONFIG_QCM_GCC_2290=y >>>> CONFIG_QCM_DISPCC_2290=m >>>> CONFIG_QCS_GCC_404=y >>>> +CONFIG_QCS_GCC_8300=y >>>> CONFIG_QDU_GCC_1000=y >>>> CONFIG_SC_CAMCC_8280XP=m >>>> CONFIG_SC_DISPCC_7280=m >>>> @@ -1618,6 +1620,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y >>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >>>> CONFIG_INTERCONNECT_QCOM_QCM2290=y >>>> CONFIG_INTERCONNECT_QCOM_QCS404=m >>>> +CONFIG_INTERCONNECT_QCOM_QCS8300=y >>> >>> Why this cannot be a module? >>> >>> >> I think the commit-msg "It needs to be built-in for UART to provide a console." can >> explain that, could you please help to share your insights on that? > > Unless loading these modules from initramfs doesn't work, please use =m. > The drivers that are enabled here are going to be enabled for everybody > using arm64 defconfig, taking up memory on their platforms, etc. > We had previous discussion here about why these drivers needs to be built-in to support debug-uart: https://lore.kernel.org/linux-arm-msm/c11fd3c2-770a-4d40-8cf3-d8bc81f7c480@kernel.org/ I will mention more details in the commit message of this patch. Thanks, Jingyi
On Fri, 6 Sept 2024 at 09:15, Jingyi Wang <quic_jingyw@quicinc.com> wrote: > > Hi Dmitry, > > On 9/6/2024 11:18 AM, Dmitry Baryshkov wrote: > > On Thu, Sep 05, 2024 at 12:54:35PM GMT, Jingyi Wang wrote: > >> > >> > >> On 9/4/2024 5:39 PM, Krzysztof Kozlowski wrote: > >>> On 04/09/2024 10:33, Jingyi Wang wrote: > >>>> Enable clock controller, interrconnect and pinctrl for QCS8300. > >>> > >>> NXP QCS8300? What is QCS8300? Which products use it? That's a defconfig > >>> for entire kernel, not your Qualcomm one. > >>> > >> Will describe it in more detail. > >>>> It needs to be built-in for UART to provide a console. > >>>> > >>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> > >>>> --- > >>>> arch/arm64/configs/defconfig | 3 +++ > >>>> 1 file changed, 3 insertions(+) > >>>> > >>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > >>>> index 81ca46e3ab4b..a9ba6b25a0ed 100644 > >>>> --- a/arch/arm64/configs/defconfig > >>>> +++ b/arch/arm64/configs/defconfig > >>>> @@ -606,6 +606,7 @@ CONFIG_PINCTRL_MSM8996=y > >>>> CONFIG_PINCTRL_MSM8998=y > >>>> CONFIG_PINCTRL_QCM2290=y > >>>> CONFIG_PINCTRL_QCS404=y > >>>> +CONFIG_PINCTRL_QCS8300=y > >>>> CONFIG_PINCTRL_QDF2XXX=y > >>>> CONFIG_PINCTRL_QDU1000=y > >>>> CONFIG_PINCTRL_SA8775P=y > >>>> @@ -1317,6 +1318,7 @@ CONFIG_MSM_MMCC_8998=m > >>>> CONFIG_QCM_GCC_2290=y > >>>> CONFIG_QCM_DISPCC_2290=m > >>>> CONFIG_QCS_GCC_404=y > >>>> +CONFIG_QCS_GCC_8300=y > >>>> CONFIG_QDU_GCC_1000=y > >>>> CONFIG_SC_CAMCC_8280XP=m > >>>> CONFIG_SC_DISPCC_7280=m > >>>> @@ -1618,6 +1620,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y > >>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m > >>>> CONFIG_INTERCONNECT_QCOM_QCM2290=y > >>>> CONFIG_INTERCONNECT_QCOM_QCS404=m > >>>> +CONFIG_INTERCONNECT_QCOM_QCS8300=y > >>> > >>> Why this cannot be a module? > >>> > >>> > >> I think the commit-msg "It needs to be built-in for UART to provide a console." can > >> explain that, could you please help to share your insights on that? > > > > Unless loading these modules from initramfs doesn't work, please use =m. > > The drivers that are enabled here are going to be enabled for everybody > > using arm64 defconfig, taking up memory on their platforms, etc. > > > We had previous discussion here about why these drivers needs to be built-in to support > debug-uart: > https://lore.kernel.org/linux-arm-msm/c11fd3c2-770a-4d40-8cf3-d8bc81f7c480@kernel.org/ > I will mention more details in the commit message of this patch. Yes, please. Explicitly mention that this is required to get UART to work.
Add initial support for QCS8300 SoC and QCS8300 RIDE board. This revision brings support for: - CPUs with cpu idle - interrupt-controller with PDC wakeup support - gcc - TLMM - interconnect - qup with uart - smmu - pmic - ufs - ipcc - sram - remoteprocs including ADSP,CDSP and GPDSP Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> --- patch series organized as: - 1-2: remoteproc binding and driver - 3-5: ufs binding and driver - 6-7: rpmhpd binding and driver - 8-15: bindings for other components found on the SoC - 16-19: changes to support the device tree dependencies: tlmm: https://lore.kernel.org/linux-arm-msm/20240819064933.1778204-1-quic_jingyw@quicinc.com/ gcc: https://lore.kernel.org/all/20240820-qcs8300-gcc-v1-0-d81720517a82@quicinc.com/ interconnect: https://lore.kernel.org/linux-arm-msm/20240827151622.305-1-quic_rlaggysh@quicinc.com/ dtb check got following err: /local/mnt/workspace/jingyi/aim500/linux/arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: interconnect@1680000: Unevaluated properties are not allowed ('reg' was unexpected) which is cause by "reg" compatible missing in dt binding, will be fixed in interconnect patch series. --- Jingyi Wang (11): dt-bindings: remoteproc: qcom,sa8775p-pas: Document QCS8300 remoteproc remoteproc: qcom: pas: Add QCS8300 remoteproc support dt-bindings: qcom,pdc: document QCS8300 Power Domain Controller dt-bindings: soc: qcom: add qcom,qcs8300-imem compatible dt-bindings: mailbox: qcom-ipcc: Document QCS8300 IPCC dt-bindings: mfd: qcom,tcsr: Add compatible for QCS8300 dt-bindings: nvmem: qfprom: Add compatible for QCS8300 dt-bindings: arm: qcom: document QCS8275/QCS8300 SoC and reference board arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 arm64: dts: qcom: add initial support for QCS8300 DTSI arm64: dts: qcom: add base QCS8300 RIDE dts Kyle Deng (1): dt-bindings: soc: qcom,aoss-qmp: Document the QCS8300 AOSS channel Shazad Hussain (1): dt-bindings: power: rpmpd: Add QCS8300 power domains Tingguo Cheng (1): pmdomain: qcom: rpmhpd: Add QCS8300 power domains Xin Liu (3): dt-bindings: phy: Add QMP UFS PHY comptible for QCS8300 dt-bindings: ufs: qcom: Document the QCS8300 UFS Controller phy: qcom-qmp-ufs: Add support for QCS8300 Zhenhua Huang (2): dt-bindings: arm-smmu: Add compatible for QCS8300 SoC dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs Documentation/devicetree/bindings/arm/qcom.yaml | 8 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + .../bindings/interrupt-controller/qcom,pdc.yaml | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml | 2 + .../devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + .../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + .../devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + .../bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 + .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + .../bindings/remoteproc/qcom,sa8775p-pas.yaml | 6 + .../bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + .../devicetree/bindings/sram/qcom,imem.yaml | 1 + .../devicetree/bindings/ufs/qcom,ufs.yaml | 2 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 246 ++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1282 ++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 + drivers/pmdomain/qcom/rpmhpd.c | 24 + drivers/remoteproc/qcom_q6v5_pas.c | 3 + include/dt-bindings/power/qcom-rpmpd.h | 19 + 21 files changed, 1609 insertions(+) --- base-commit: eb8c5ca373cbb018a84eb4db25c863302c9b6314 change-id: 20240829-qcs8300_initial_dtsi-1a386eb317d3 Best regards,