| Message ID | 20241010070510.1504250-2-quic_mdalam@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add QPIC SPI NAND driver | expand |
On Thu, 10 Oct 2024 12:35:03 +0530, Md Sadre Alam wrote: > Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. > It can work both in serial and parallel mode and supports typical > SPI-NAND page cache operations. > > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- > > Change in [v11] > > * Dropped Reviewed-by tag > * Added Soc based compitable "qcom,ipq9574-snand" > > Change in [v10] > > * No change > > Change in [v9] > > * No change > > Change in [v8] > > * No change > > Change in [v7] > > * No change > > Change in [v6] > > * No change > > Change in [v5] > > * No change > > Change in [v4] > > * Fix spelling mistake in HW description > > * Added commit message > > * Removed '|' from description > > * Removed minItems in clock > > * Added blank line > > * Removed co-developed by > > Change in [v3] > > * Updated commit message, removed "dt-bindings" from commit > message > > * Updated compatible name as file name > > * Added hardware description > > * Documented clock-name > > * Moved dma-names property to top > > * Droped unused label "qpic_nand" > > * Fixed indentation in example dt node > > Change in [v2] > > * Added initial support for dt-bindings > > Change in [v1] > > * This patch was not included in [v1] > > .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
On 10/10/2024 09:05, Md Sadre Alam wrote: > Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. > It can work both in serial and parallel mode and supports typical > SPI-NAND page cache operations. > > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 000000000000..aa3f93319203 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam <quic_mdalam@quicinc.com> + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,ipq9574-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; + };
Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. It can work both in serial and parallel mode and supports typical SPI-NAND page cache operations. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> --- Change in [v11] * Dropped Reviewed-by tag * Added Soc based compitable "qcom,ipq9574-snand" Change in [v10] * No change Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * Fix spelling mistake in HW description * Added commit message * Removed '|' from description * Removed minItems in clock * Added blank line * Removed co-developed by Change in [v3] * Updated commit message, removed "dt-bindings" from commit message * Updated compatible name as file name * Added hardware description * Documented clock-name * Moved dma-names property to top * Droped unused label "qpic_nand" * Fixed indentation in example dt node Change in [v2] * Added initial support for dt-bindings Change in [v1] * This patch was not included in [v1] .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml