| Message ID | 20241009-x1e80100-dts-fixes-pcie6a-v3-1-14a1163e691b@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description | expand |
On Wed, 09 Oct 2024 14:07:23 +0300, Abel Vesa wrote: > Fix the description and compatible for PCIe 6a, as it is in fact a > 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For > 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode, > PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number > of lanes in which the PHY should be configured depends on a TCSR register > value on each individual board. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description commit: 837c333f46df8ce6755ba82c53acb91948ec0072 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..4ec712cb7a26d8fe434631cf15949524fd22c7d9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2931,7 +2931,7 @@ pcie6a: pci@1bf8000 { dma-coherent; linux,pci-domain = <6>; - num-lanes = <2>; + num-lanes = <4>; interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, @@ -2997,8 +2997,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, }; pcie6a_phy: phy@1bfc000 { - compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; - reg = <0 0x01bfc000 0 0x2000>; + compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; + reg = <0 0x01bfc000 0 0x2000>, + <0 0x01bfe000 0 0x2000>; clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, @@ -3021,6 +3022,8 @@ pcie6a_phy: phy@1bfc000 { power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + qcom,4ln-config-sel = <&tcsr 0x1a000 0>; + #clock-cells = <0>; clock-output-names = "pcie6a_pipe_clk";
Fix the description and compatible for PCIe 6a, as it is in fact a 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number of lanes in which the PHY should be configured depends on a TCSR register value on each individual board. Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- Changes in v3: - Re-worded the commit message once more to suggest a fix w.r.t lanes. - Added back fixes tag and CC stable but with noautosel reason - Picked up Konrad's R-b tag. - Link to v2: https://lore.kernel.org/r/20241004-x1e80100-dts-fixes-pcie6a-v2-1-3af9ff7a5a71@linaro.org Changes in v2: - Re-worded the commit message according to Johan's suggestions - Dropped the clocks changes. - Dropped the fixes tag as this relies on the Gen4 4-lanes stability patchset which has been only merged in 6.12, so backporting this patch would break NVMe support for all platforms. - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@linaro.org --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) --- base-commit: c02d24a5af66a9806922391493205a344749f2c4 change-id: 20241003-x1e80100-dts-fixes-pcie6a-b9f1171e8d5b Best regards,