| Message ID | 20241018141332.942844-6-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | docs/system/arm: Provide at least skeleton docs for all boards | expand |
On Sat, Oct 19, 2024 at 12:15 AM Peter Maydell <peter.maydell@linaro.org> wrote: > > Add a placeholder doc for the xlnx-zcu102 board. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > MAINTAINERS | 1 + > docs/system/arm/xlnx-zcu102.rst | 19 +++++++++++++++++++ > docs/system/target-arm.rst | 1 + > 3 files changed, 21 insertions(+) > create mode 100644 docs/system/arm/xlnx-zcu102.rst > > diff --git a/MAINTAINERS b/MAINTAINERS > index 031b117a3a0..7c3325628c9 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1016,6 +1016,7 @@ F: include/hw/ssi/xilinx_spips.h > F: hw/display/dpcd.c > F: include/hw/display/dpcd.h > F: docs/system/arm/xlnx-versal-virt.rst > +F: docs/system/arm/xlnx-zcu102.rst > > Xilinx Versal OSPI > M: Francisco Iglesias <francisco.iglesias@amd.com> > diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst > new file mode 100644 > index 00000000000..534cd1dc887 > --- /dev/null > +++ b/docs/system/arm/xlnx-zcu102.rst > @@ -0,0 +1,19 @@ > +Xilinx ZynqMP ZCU102 (``xlnx-zcu102``) > +====================================== > + > +The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board. > +This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs. > + > +Machine-specific options > +"""""""""""""""""""""""" > + > +The following machine-specific options are supported: > + > +secure > + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the > + Arm Security Extensions (TrustZone). The default is ``off``. > + > +virtualization > + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the > + Arm Virtualization Extensions. The default is ``off``. > + > diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst > index a7f88c8f317..ace36d1b17d 100644 > --- a/docs/system/target-arm.rst > +++ b/docs/system/target-arm.rst > @@ -107,6 +107,7 @@ undocumented; you can get a complete list by running > arm/xenpvh > arm/xlnx-versal-virt > arm/xlnx-zynq > + arm/xlnx-zcu102 > > Emulated CPU architecture support > ================================= > -- > 2.34.1 > >
diff --git a/MAINTAINERS b/MAINTAINERS index 031b117a3a0..7c3325628c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1016,6 +1016,7 @@ F: include/hw/ssi/xilinx_spips.h F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst +F: docs/system/arm/xlnx-zcu102.rst Xilinx Versal OSPI M: Francisco Iglesias <francisco.iglesias@amd.com> diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst new file mode 100644 index 00000000000..534cd1dc887 --- /dev/null +++ b/docs/system/arm/xlnx-zcu102.rst @@ -0,0 +1,19 @@ +Xilinx ZynqMP ZCU102 (``xlnx-zcu102``) +====================================== + +The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board. +This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +secure + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Security Extensions (TrustZone). The default is ``off``. + +virtualization + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Virtualization Extensions. The default is ``off``. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index a7f88c8f317..ace36d1b17d 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -107,6 +107,7 @@ undocumented; you can get a complete list by running arm/xenpvh arm/xlnx-versal-virt arm/xlnx-zynq + arm/xlnx-zcu102 Emulated CPU architecture support =================================
Add a placeholder doc for the xlnx-zcu102 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- MAINTAINERS | 1 + docs/system/arm/xlnx-zcu102.rst | 19 +++++++++++++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 21 insertions(+) create mode 100644 docs/system/arm/xlnx-zcu102.rst