| Message ID | 20250418-topic-sm8x50-upstream-iris-8650-dt-v1-1-80a6ae50bf10@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sm8650: add iris DT node | expand |
On Fri, 18 Apr 2025 15:20:35 +0200, Neil Armstrong wrote: > Add DT entries for the sm8650 iris decoder. > > Since the firmware is required to be signed, only enable > on Qualcomm development boards where the firmware is > available. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 5 ++ > arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 5 ++ > arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 5 ++ > arch/arm64/boot/dts/qcom/sm8650.dtsi | 94 +++++++++++++++++++++++++++++++++ > 4 files changed, 109 insertions(+) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: base-commit a7dca088884312d607fff89f2666c670cb7073ac not known, ignoring Base: attempting to guess base-commit... Base: tags/next-20250417 (exact match) If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250418-topic-sm8x50-upstream-iris-8650-dt-v1-1-80a6ae50bf10@linaro.org: arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8650-iris'] arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8650-iris'] arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: /soc@0/video-codec@aa00000: failed to match any schema with compatible: ['qcom,sm8650-iris']
On 19/04/2025 01:05, Dmitry Baryshkov wrote: > On Fri, Apr 18, 2025 at 03:20:35PM +0200, Neil Armstrong wrote: >> Add DT entries for the sm8650 iris decoder. >> >> Since the firmware is required to be signed, only enable >> on Qualcomm development boards where the firmware is >> available. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 5 ++ >> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 5 ++ >> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 5 ++ > > I'd say that these are 4 commits. I could make 10 and still be coherent, but do we really need 4 here ? > >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 94 +++++++++++++++++++++++++++++++++ >> 4 files changed, 109 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts >> index d0912735b54e5090f9f213c2c9341e03effbbbff..69db971d9d2d32cdee7bb1c3093c7849b94798a0 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts >> @@ -894,6 +894,11 @@ &ipa { >> status = "okay"; >> }; >> >> +&iris { >> + firmware-name = "qcom/vpu/vpu33_p4.mbn"; > > You shouldn't need to specify this, it matches the default one. Hmm ok > >> + status = "okay"; >> +}; >> + >> &gpu { >> status = "okay"; >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts >> index 76ef43c10f77d8329ccf0a05c9d590a46372315f..04108235d9bc6f977e9cf1b887b0c89537723387 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts >> @@ -585,6 +585,11 @@ vreg_l7n_3p3: ldo7 { >> }; >> }; >> >> +&iris { >> + firmware-name = "qcom/vpu/vpu33_p4.mbn"; >> + status = "okay"; >> +}; >> + >> &lpass_tlmm { >> spkr_1_sd_n_active: spkr-1-sd-n-active-state { >> pins = "gpio21"; >> diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts >> index 71033fba21b56bc63620dca3e453c14191739675..58bdc6619ac55eda122f3fe6e680e0e61967d019 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts >> @@ -824,6 +824,11 @@ &ipa { >> status = "okay"; >> }; >> >> +&iris { >> + firmware-name = "qcom/vpu/vpu33_p4.mbn"; >> + status = "okay"; >> +}; >> + >> &gpu { >> status = "okay"; >> > Thanks, Neil
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index d0912735b54e5090f9f213c2c9341e03effbbbff..69db971d9d2d32cdee7bb1c3093c7849b94798a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -894,6 +894,11 @@ &ipa { status = "okay"; }; +&iris { + firmware-name = "qcom/vpu/vpu33_p4.mbn"; + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 76ef43c10f77d8329ccf0a05c9d590a46372315f..04108235d9bc6f977e9cf1b887b0c89537723387 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -585,6 +585,11 @@ vreg_l7n_3p3: ldo7 { }; }; +&iris { + firmware-name = "qcom/vpu/vpu33_p4.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 71033fba21b56bc63620dca3e453c14191739675..58bdc6619ac55eda122f3fe6e680e0e61967d019 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -824,6 +824,11 @@ &ipa { status = "okay"; }; +&iris { + firmware-name = "qcom/vpu/vpu33_p4.mbn"; + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c2937f7217943c4ca91a91eadc8259b2d6a01372..9afde0582ec9b8fef44c0af0324bfae9b20d1d60 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4955,6 +4955,100 @@ opp-202000000 { }; }; + iris: video-codec@aa00000 { + compatible = "qcom,sm8650-iris"; + reg = <0 0x0aa00000 0 0xf0000>; + + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + operating-points-v2 = <&iris_opp_table>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + /* FW load region */ + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "bus", + "xo", + "core"; + + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-196000000 { + opp-hz = /bits/ 64 <196000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sm8650-videocc"; reg = <0 0x0aaf0000 0 0x10000>;
Add DT entries for the sm8650 iris decoder. Since the firmware is required to be signed, only enable on Qualcomm development boards where the firmware is available. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 5 ++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 94 +++++++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+) --- base-commit: a7dca088884312d607fff89f2666c670cb7073ac change-id: 20250418-topic-sm8x50-upstream-iris-8650-dt-d2c64a59505f Best regards,