From patchwork Thu Oct 26 19:06:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 117253 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1123918qgn; Thu, 26 Oct 2017 12:07:35 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QkokBMVjK48/D5K6ANH/L9duICMuk3zS7VkSpFbD0Gt9WfLQK0PuvFV6wtDT+Ti3Vs4Fdz X-Received: by 10.159.253.6 with SMTP id p6mr5089984pls.212.1509044855715; Thu, 26 Oct 2017 12:07:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509044855; cv=none; d=google.com; s=arc-20160816; b=tuJSNyZIdqvsknPytnvnmMvmp+VpNFbxrPaCKJoPpqZxNf7CFMIEc0TiAzyxzbzBqt yb9tcq5sA0UUO8DXPUCA5zeP1xTYwQLaZX3Vr1coVJsaVnG22hMzK1qHFalj3RMIH0mw QulV3miX27hore18t+7CHar+DRgqR4LSpeVK+tVG8Vmyyz0pX94hE1CqVdlXj3N79dai yNG11wCW0osZia89aLPZt6IrAHnmyI6T9VNF0m56ZRSWo88vQPOnJJF6W53UOhcGVwRo +2g1OpITicnUuqyRTdXDahANy7GxBKuVyNWTl/z9ICY3MI4qoZNHvgvv+KqxbaC25kLz vNOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:to:from:delivered-to:sender:list-help :list-post:list-archive:list-subscribe:list-unsubscribe:list-id :precedence:mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=W7Wq5e0E7vvqkqg/F7nw4V1JoKXBWWHMwl40FoskRpU=; b=gvd9Kw7hpe+J8GkIAAr8bDX8OifY5rwGP2tuXKm+excTdM1h1M0bQC3G2ivSbgmFEY g/2BykTM18m+Pe9bVLToQr8h8QrEP25Ysbg28kjyvPtu/N63z8a0aCTit7gYZZQs5UxT duTdcUZCUU8ap6MKvdL8AXkviPeUqyO2OUmoj0FqeHfUy7ycrJPu5ywqYk+dfU6HUERt OWanF/Wk8IuBnPsy1ZadsK9emrHypJ9ShPW9RXn4rXENL5y4MP6ghS6eCj9nwrlASEQA 9o4JIQLEJGzRXaCyLIzLvxOavMJniqs/lHdyJToRJY+sMRbfVb9pyU1+z5LmqHmKH+f5 qYcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wlqQH9p+; spf=pass (google.com: domain of libc-alpha-return-86403-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-86403-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id a3si3341286pla.160.2017.10.26.12.07.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 12:07:35 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-86403-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wlqQH9p+; spf=pass (google.com: domain of libc-alpha-return-86403-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-86403-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; q=dns; s= default; b=Ux32rzsKDiLSK5a/HkfvyBK8cXWu8ctOpLuhSJ+iiiLW1uUNfYWVL pbk9iNtGrn2Ld5Ti1l5oRfkxnF13552JZhCY55pcc+R9pgrLGnUJrEu5kjeTRzUc V4f29AhCed234YhqP06acuUyKyksE7I82fX4WSAYYE5yIt3Gdh4+jQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; s=default; bh=A+zKt4VbCqgLSLESeC76BVwjtQk=; b=wlqQH9p+IuIHIfIcgVuzt4FR8n9h oL8qvvLIxbOS+a/9JvMOxLAkQpMfowle8jbk0kwZ9ENHar3jfD2U7HjkZFcv9EbK v0VP1VhMZBm2RnkWoFUP1Bw4BRxA5kMl9UQ4uMhd3dn/UZHE2VrI6b3jNe53iKau 14bvlYW6s6KkQ70= Received: (qmail 96853 invoked by alias); 26 Oct 2017 19:07:06 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 96827 invoked by uid 89); 26 Oct 2017 19:07:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-8.6 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=ham version=3.3.2 spammy= X-HELO: mail-qt0-f193.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=W7Wq5e0E7vvqkqg/F7nw4V1JoKXBWWHMwl40FoskRpU=; b=CSuaPA5HzIoJrFwvXd8PlkREhA9XlgmE4wKomMNP55XbuNAuKAu0IsWQjJ2jjTtoaj 7W8eVGw8Dvcobi5iDsGEk2eA9j1XsmW+YRBy14sthadXgs2t46+At0NKbriqlpi2bFCD yj5NRK4MjaYwhWkSw5J/4EZkeXawo/SxngTYN9/mj7G84TMSHIKjyiLV/kGEtXEKEiEV 0D2MIguJoYwk/4VLSqtg0Nx6Anej7GpXbR3uIZ8LF0btnPH9JHwAV9zbnpoforjUBpwe w/aQbSh/tF56Ehr8irA+t6eeTF3/zELQKuGl1/+eZzrHsERQgpptvwG6jBrkpX1KLDPY eHOg== X-Gm-Message-State: AMCzsaVQGVHY0dSkbHAqEaS2d/yyLwsEwN7Vy99iU6jGy3iJ9Uzc9G7W j4mnuNS1LR0OBWyZU6wNA+NKFb43jFk= X-Received: by 10.200.43.193 with SMTP id n1mr35882250qtn.101.1509044819701; Thu, 26 Oct 2017 12:06:59 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 00/25] Refactor IFUNC selection in C Date: Thu, 26 Oct 2017 17:06:28 -0200 Message-Id: <1509044813-9951-1-git-send-email-adhemerval.zanella@linaro.org> This patchset is the continuation of two previous patchset [1][2][3][4] to convert ifunc implementation in assembly to C using GLIBC macros (which may use direct asm or GCC attributes depending of compiler support). No functional change is expected in generated symbols or ifunc selection, although some code reorganization was done in the case of ifunc selection also build the default variant at the same module. In this case a new file is created with 'generic' suffix. I also created a personal branch for this patchset on azanella/ifunc-c [5] [1] https://sourceware.org/ml/libc-alpha/2017-10/msg00578.html [2] https://sourceware.org/ml/libc-alpha/2017-10/msg00576.html [3] https://sourceware.org/ml/libc-alpha/2017-10/msg00281.html [4] https://sourceware.org/ml/libc-alpha/2017-10/msg00282.html [5] https://sourceware.org/git/?p=glibc.git;a=shortlog;h=refs/heads/azanella/ifunc-c Adhemerval Zanella (25): arm: Implement memcpy ifunc selection in C arm: Implement memchr ifunc selection in C sparc: Implement memcpy/mempcpy ifunc selection in C sparc: Implement memset/bzero ifunc selection in C sparc: Assume VIS3 support sparc: refactor sparc64 signbit{f} selector to C sparc: refactor sparc64 isnan{f} selector to C sparc: refactor sparc64 isinf{f} selector to C sparc: refactor sparc64 finite{f} selector to C sparc: refactor sparc64 nearbyint{f} selector to C sparc: refactor sparc64 lrint{f} selector to C sparc: refactor sparc64 rint{f} selector to C sparc: refactor sparc64 __mpn_mul_1 selector to C sparc: refactor sparc64 __mpn_sub_n selector to C sparc: refactor sparc64 __mpn_addmul_1 selector to C sparc: refactor sparc64 __mpn_submul_1 selector to C sparc: refactor sparc64 __mpn_add_n selector to C sparc: refactor sparc32 copysign selector to C sparc: refactor sparc32 fabs{f} selector to C sparc: refactor sparc32 llrint{f} selector to C sparc: refactor sparc32 rint{f} selector to C sparc: refactor sparc32 nearbyint{f} selector to C sparc: refactor cpu_relax to C sparc: Remove ununsed ifunc assembly macros x32: Remove unused getcpu implementation ChangeLog | 279 +++++++++++++++++++++ config.h.in | 3 - sysdeps/arm/arm-ifunc.h | 33 +++ sysdeps/arm/armv7/multiarch/Makefile | 3 +- sysdeps/arm/armv7/multiarch/ifunc-memchr.h | 28 +++ sysdeps/arm/armv7/multiarch/ifunc-memcpy.h | 37 +++ sysdeps/arm/armv7/multiarch/memchr.c | 35 +++ sysdeps/arm/armv7/multiarch/memchr_impl.S | 219 ---------------- sysdeps/arm/armv7/multiarch/memchr_neon.S | 221 +++++++++++++++- sysdeps/arm/armv7/multiarch/memchr_noneon.S | 5 + sysdeps/arm/armv7/multiarch/memcpy.S | 76 ------ sysdeps/arm/armv7/multiarch/memcpy.c | 35 +++ sysdeps/arm/armv7/multiarch/memcpy_arm.S | 10 + sysdeps/arm/armv7/multiarch/memcpy_neon.S | 8 +- sysdeps/arm/armv7/multiarch/memcpy_vfp.S | 4 +- sysdeps/arm/armv7/multiarch/rtld-memchr.S | 1 + sysdeps/arm/armv7/multiarch/rtld-memcpy.S | 1 + sysdeps/sparc/configure | 42 ---- sysdeps/sparc/configure.ac | 29 --- sysdeps/sparc/sparc-ifunc.h | 163 ++---------- sysdeps/sparc/sparc32/sparcv9/Makefile | 7 - sysdeps/sparc/sparc32/sparcv9/cpu_relax.S | 1 - sysdeps/sparc/sparc32/sparcv9/cpu_relax.c | 1 + .../sparc/sparc32/sparcv9/fpu/multiarch/Makefile | 26 +- .../sparcv9/fpu/multiarch/s_copysign-generic.S | 8 + .../sparc32/sparcv9/fpu/multiarch/s_copysign.S | 21 -- .../sparc32/sparcv9/fpu/multiarch/s_copysign.c | 38 +++ .../sparcv9/fpu/multiarch/s_copysignf-generic.S | 4 + .../sparc32/sparcv9/fpu/multiarch/s_copysignf.S | 12 - .../sparc32/sparcv9/fpu/multiarch/s_copysignf.c | 11 + .../sparc32/sparcv9/fpu/multiarch/s_fabs-generic.S | 8 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S | 18 -- .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.c | 35 +++ .../sparcv9/fpu/multiarch/s_fabsf-generic.S | 4 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S | 12 - .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.c | 29 +++ .../sparc32/sparcv9/fpu/multiarch/s_fdim-generic.c | 4 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.c | 17 +- .../sparcv9/fpu/multiarch/s_fdimf-generic.c | 3 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.c | 12 +- .../sparc32/sparcv9/fpu/multiarch/s_fma-generic.c | 2 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fma.c | 12 +- .../sparc32/sparcv9/fpu/multiarch/s_fmaf-generic.c | 2 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf.c | 10 +- .../sparcv9/fpu/multiarch/s_llrint-generic.S | 8 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S | 24 -- .../sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.c | 36 +++ .../sparcv9/fpu/multiarch/s_llrintf-generic.S | 4 + .../sparc32/sparcv9/fpu/multiarch/s_llrintf.S | 17 -- .../sparc32/sparcv9/fpu/multiarch/s_llrintf.c | 29 +++ .../sparcv9/fpu/multiarch/s_nearbyint-generic.S | 9 + .../sparc32/sparcv9/fpu/multiarch/s_nearbyint.S | 19 -- .../sparc32/sparcv9/fpu/multiarch/s_nearbyint.c | 35 +++ .../sparcv9/fpu/multiarch/s_nearbyintf-generic.S | 4 + .../sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S | 12 - .../sparc32/sparcv9/fpu/multiarch/s_nearbyintf.c | 29 +++ .../sparc32/sparcv9/fpu/multiarch/s_rint-generic.S | 8 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S | 19 -- .../sparc/sparc32/sparcv9/fpu/multiarch/s_rint.c | 35 +++ .../sparcv9/fpu/multiarch/s_rintf-generic.S | 4 + .../sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S | 12 - .../sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.c | 29 +++ sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile | 3 +- .../sparc32/sparcv9/multiarch/memcpy-ultra1.S | 32 +++ sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy.S | 4 - sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy.c | 1 + sysdeps/sparc/sparc32/sparcv9/multiarch/mempcpy.c | 1 + .../sparc32/sparcv9/multiarch/memset-ultra1.S | 30 +++ sysdeps/sparc/sparc32/sparcv9/multiarch/memset.S | 4 - sysdeps/sparc/sparc32/sparcv9/multiarch/memset.c | 1 + .../sparc/sparc32/sparcv9/multiarch/rtld-mempcpy.S | 1 + sysdeps/sparc/sparc64/Makefile | 2 - sysdeps/sparc/sparc64/cpu_relax.S | 67 ----- sysdeps/sparc/sparc64/cpu_relax.c | 38 +++ sysdeps/sparc/sparc64/fpu/multiarch/Makefile | 32 ++- .../sparc/sparc64/fpu/multiarch/s_ceil-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_ceilf-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_finite-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_finite.c | 37 +++ .../sparc64/fpu/multiarch/s_finitef-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.c | 33 +++ .../sparc/sparc64/fpu/multiarch/s_floor-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_floor.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_floorf-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_fma-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_fma.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_fmaf-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_isinf-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.c | 37 +++ .../sparc/sparc64/fpu/multiarch/s_isinff-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.c | 33 +++ .../sparc/sparc64/fpu/multiarch/s_isnan-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.c | 37 +++ .../sparc/sparc64/fpu/multiarch/s_isnanf-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S | 15 -- sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.c | 33 +++ .../sparc/sparc64/fpu/multiarch/s_lrint-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S | 17 -- sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.c | 39 +++ .../sparc/sparc64/fpu/multiarch/s_lrintf-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S | 17 -- sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.c | 39 +++ .../sparc64/fpu/multiarch/s_nearbyint-generic.S | 4 + sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S | 12 - sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.c | 29 +++ .../sparc64/fpu/multiarch/s_nearbyintf-generic.S | 4 + sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S | 12 - sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.c | 29 +++ .../sparc/sparc64/fpu/multiarch/s_rint-generic.S | 4 + sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S | 12 - sysdeps/sparc/sparc64/fpu/multiarch/s_rint.c | 29 +++ .../sparc/sparc64/fpu/multiarch/s_rintf-generic.S | 4 + sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S | 12 - sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.c | 29 +++ .../sparc64/fpu/multiarch/s_signbit-generic.S | 6 + sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S | 20 -- sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.c | 37 +++ .../sparc64/fpu/multiarch/s_signbitf-generic.S | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S | 10 - sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.c | 28 +++ .../sparc/sparc64/fpu/multiarch/s_trunc-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.c | 19 +- .../sparc/sparc64/fpu/multiarch/s_truncf-generic.c | 2 + sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.c | 19 +- sysdeps/sparc/sparc64/multiarch/Makefile | 7 +- sysdeps/sparc/sparc64/multiarch/add_n-generic.S | 2 + sysdeps/sparc/sparc64/multiarch/add_n.S | 56 ----- sysdeps/sparc/sparc64/multiarch/add_n.c | 28 +++ sysdeps/sparc/sparc64/multiarch/addmul_1-generic.S | 2 + sysdeps/sparc/sparc64/multiarch/addmul_1.S | 56 ----- sysdeps/sparc/sparc64/multiarch/addmul_1.c | 28 +++ sysdeps/sparc/sparc64/multiarch/ifunc-memcpy.h | 40 +++ sysdeps/sparc/sparc64/multiarch/ifunc-memset.h | 34 +++ .../sparc64/multiarch/memcpy-ultra1.S} | 38 +-- sysdeps/sparc/sparc64/multiarch/memcpy.S | 167 ------------ sysdeps/sparc/sparc64/multiarch/memcpy.c | 33 +++ sysdeps/sparc/sparc64/multiarch/mempcpy.c | 39 +++ .../sparc64/multiarch/memset-ultra1.S} | 23 +- sysdeps/sparc/sparc64/multiarch/memset.S | 124 --------- sysdeps/sparc/sparc64/multiarch/memset.c | 42 ++++ sysdeps/sparc/sparc64/multiarch/mul_1-generic.S | 2 + sysdeps/sparc/sparc64/multiarch/mul_1.S | 56 ----- sysdeps/sparc/sparc64/multiarch/mul_1.c | 28 +++ sysdeps/sparc/sparc64/multiarch/rtld-mempcpy.S | 1 + sysdeps/sparc/sparc64/multiarch/sub_n-generic.S | 2 + sysdeps/sparc/sparc64/multiarch/sub_n.S | 56 ----- sysdeps/sparc/sparc64/multiarch/sub_n.c | 28 +++ sysdeps/sparc/sparc64/multiarch/submul_1-generic.S | 2 + sysdeps/sparc/sparc64/multiarch/submul_1.S | 56 ----- sysdeps/sparc/sparc64/multiarch/submul_1.c | 28 +++ 159 files changed, 2222 insertions(+), 1745 deletions(-) create mode 100644 sysdeps/arm/arm-ifunc.h create mode 100644 sysdeps/arm/armv7/multiarch/ifunc-memchr.h create mode 100644 sysdeps/arm/armv7/multiarch/ifunc-memcpy.h create mode 100644 sysdeps/arm/armv7/multiarch/memchr.c delete mode 100644 sysdeps/arm/armv7/multiarch/memchr_impl.S create mode 100644 sysdeps/arm/armv7/multiarch/memchr_noneon.S delete mode 100644 sysdeps/arm/armv7/multiarch/memcpy.S create mode 100644 sysdeps/arm/armv7/multiarch/memcpy.c create mode 100644 sysdeps/arm/armv7/multiarch/memcpy_arm.S create mode 100644 sysdeps/arm/armv7/multiarch/rtld-memchr.S create mode 100644 sysdeps/arm/armv7/multiarch/rtld-memcpy.S delete mode 100644 sysdeps/sparc/sparc32/sparcv9/cpu_relax.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/cpu_relax.c create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-generic.S delete mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.c create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-generic.S delete mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.c create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-generic.S delete mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.c create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-generic.S delete mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S create mode 100644 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