| Message ID | 20180521140402.23318-1-peter.maydell@linaro.org |
|---|---|
| Headers | show |
| Series | iommu: support txattrs, support TCG execution, implement TZ MPC | expand |
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180521140402.23318-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
5bcf917ee3..9802316ed6 master -> master
t [tag update] patchew/20180509034658.26455-1-f4bug@amsat.org -> patchew/20180509034658.26455-1-f4bug@amsat.org
* [new tag] patchew/20180521140402.23318-1-peter.maydell@linaro.org -> patchew/20180521140402.23318-1-peter.maydell@linaro.org
Switched to a new branch 'test'
19069d042c hw/arm/mps2-tz.c: Instantiate MPCs
545f7d3702 hw/arm/iotkit: Wire up MPC interrupt lines
965dcdf3c3 hw/arm/iotkit: Instantiate MPC
5aeb41635d hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS
06b812c890 hw/core/or-irq: Support more than 16 inputs to an OR gate
d29f89b59f vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
417b50c6f7 hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate
4d9bb0adb6 hw/misc/tz-mpc.c: Implement correct blocked-access behaviour
8b1bbc0790 hw/misc/tz-mpc.c: Implement registers
66fad85c8d hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller
1e200a4e8f exec.c: Handle IOMMUs in address_space_translate_for_iotlb()
1b9a2ae51d iommu: Add IOMMU index argument to translate method
b022117fca iommu: Add IOMMU index argument to notifier APIs
71890073bb iommu: Add IOMMU index concept to IOMMU API
0093540ad1 Make address_space_translate_iommu take a MemTxAttrs argument
09947170a9 Make flatview_do_translate() take a MemTxAttrs argument
8388c25d74 Make address_space_get_iotlb_entry() take a MemTxAttrs argument
4f8f7862e7 Make flatview_translate() take a MemTxAttrs argument
29b8404366 Make flatview_access_valid() take a MemTxAttrs argument
2779af384f Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
7ec3d4eee3 Make memory_region_access_valid() take a MemTxAttrs argument
2dbbe355a7 Make flatview_extend_translation() take a MemTxAttrs argument
b1a96a2a28 Make address_space_access_valid() take a MemTxAttrs argument
07fc6cedd7 Make address_space_map() take a MemTxAttrs argument
b99085d422 Make address_space_translate{, _cached}() take a MemTxAttrs argument
a8e73cc870 Make tb_invalidate_phys_addr() take a MemTxAttrs argument
c6d0746766 memory.h: Improve IOMMU related documentation
=== OUTPUT BEGIN ===
Checking PATCH 1/27: memory.h: Improve IOMMU related documentation...
Checking PATCH 2/27: Make tb_invalidate_phys_addr() take a MemTxAttrs argument...
Checking PATCH 3/27: Make address_space_translate{, _cached}() take a MemTxAttrs argument...
Checking PATCH 4/27: Make address_space_map() take a MemTxAttrs argument...
Checking PATCH 5/27: Make address_space_access_valid() take a MemTxAttrs argument...
Checking PATCH 6/27: Make flatview_extend_translation() take a MemTxAttrs argument...
Checking PATCH 7/27: Make memory_region_access_valid() take a MemTxAttrs argument...
Checking PATCH 8/27: Make MemoryRegion valid.accepts callback take a MemTxAttrs argument...
Checking PATCH 9/27: Make flatview_access_valid() take a MemTxAttrs argument...
Checking PATCH 10/27: Make flatview_translate() take a MemTxAttrs argument...
Checking PATCH 11/27: Make address_space_get_iotlb_entry() take a MemTxAttrs argument...
Checking PATCH 12/27: Make flatview_do_translate() take a MemTxAttrs argument...
Checking PATCH 13/27: Make address_space_translate_iommu take a MemTxAttrs argument...
WARNING: line over 80 characters
#30: FILE: exec.c:492:
+ AddressSpace **target_as,
total: 0 errors, 1 warnings, 32 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 14/27: iommu: Add IOMMU index concept to IOMMU API...
Checking PATCH 15/27: iommu: Add IOMMU index argument to notifier APIs...
Checking PATCH 16/27: iommu: Add IOMMU index argument to translate method...
Checking PATCH 17/27: exec.c: Handle IOMMUs in address_space_translate_for_iotlb()...
Checking PATCH 18/27: hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#81:
new file mode 100644
total: 0 errors, 1 warnings, 486 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 19/27: hw/misc/tz-mpc.c: Implement registers...
Checking PATCH 20/27: hw/misc/tz-mpc.c: Implement correct blocked-access behaviour...
Checking PATCH 21/27: hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate...
Checking PATCH 22/27: vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY...
Checking PATCH 23/27: hw/core/or-irq: Support more than 16 inputs to an OR gate...
ERROR: spaces required around that '*' (ctx:VxV)
#71: FILE: hw/core/or-irq.c:108:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 0 warnings, 62 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/27: hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS...
ERROR: spaces required around that '*' (ctx:VxV)
#92: FILE: hw/misc/iotkit-secctl.c:711:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 0 warnings, 100 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 25/27: hw/arm/iotkit: Instantiate MPC...
Checking PATCH 26/27: hw/arm/iotkit: Wire up MPC interrupt lines...
Checking PATCH 27/27: hw/arm/mps2-tz.c: Instantiate MPCs...
=== OUTPUT END ===
Test command exited with code: 1
---
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Please send your feedback to patchew-devel@redhat.com
On 21/05/2018 16:03, Peter Maydell wrote: > This patchset is a rather large one, but the first half is all > fairly simple plumbing. It does four things: > * support IOMMUs that are aware of memory transaction attributes and > may generate different translations for different attributes > * support TCG execution out of memory which is behind an IOMMU > * implement the Arm TrustZone Memory Protection Controller > (which needs both the above features in the IOMMU core code) > * use the MPC in the mps2-an505 board Go ahead and apply it through the ARM tree. Thanks! Paolo
On 30 May 2018 at 17:58, Paolo Bonzini <pbonzini@redhat.com> wrote: > On 21/05/2018 16:03, Peter Maydell wrote: >> This patchset is a rather large one, but the first half is all >> fairly simple plumbing. It does four things: >> * support IOMMUs that are aware of memory transaction attributes and >> may generate different translations for different attributes >> * support TCG execution out of memory which is behind an IOMMU >> * implement the Arm TrustZone Memory Protection Controller >> (which needs both the above features in the IOMMU core code) >> * use the MPC in the mps2-an505 board > > Go ahead and apply it through the ARM tree. Thanks! It needs a v2 (there are some patches that need fixing), and some of the tail end of the patchset hasn't been reviewed, and I'm not sure if we have consensus on the IOMMU API changes completely yet. But if you're happy we're going in the right direction I can apply 1-13 via target-arm.next (that's the "plumb TxAttrs through various functions" patches). That will reduce the size of the patchset and make conflicts less likely. thanks -- PMM
On 31 May 2018 at 10:54, Peter Maydell <peter.maydell@linaro.org> wrote: > On 30 May 2018 at 17:58, Paolo Bonzini <pbonzini@redhat.com> wrote: >> Go ahead and apply it through the ARM tree. Thanks! > > It needs a v2 (there are some patches that need fixing), > and some of the tail end of the patchset hasn't been reviewed, > and I'm not sure if we have consensus on the IOMMU API changes > completely yet. But if you're happy we're going in the right > direction I can apply 1-13 via target-arm.next (that's the > "plumb TxAttrs through various functions" patches). That will > reduce the size of the patchset and make conflicts less likely. I'm putting patches 1-13 (initial plumbing) and 22 (adding VMSTATE_BOOL_SUB_ARRAY) into target-arm.next. The rest will need a respin to fix minor nits and some conflicts with things that are now in master. thanks -- PMM
This patchset is a rather large one, but the first half is all fairly simple plumbing. It does four things: * support IOMMUs that are aware of memory transaction attributes and may generate different translations for different attributes * support TCG execution out of memory which is behind an IOMMU * implement the Arm TrustZone Memory Protection Controller (which needs both the above features in the IOMMU core code) * use the MPC in the mps2-an505 board I'm happy to split this up (eg taking the IOMMU core code changes through Paolo's tree and then the MPS stuff via target-arm), but I figured it would be useful to see the reason and the user of the new APIs in the same series. Patch 1 is my "improve the IOMMU API documentation" patch (included here because otherwise the added API documentation for new methods would conflict). Patches 2-13 are the boring plumbing: we pass down MemTxAttrs through enough of the memory subsystem that we have access to them at the point where we call the IOMMU translate method. (A previous version of these was posted separately; I've rebased them and updated to account for new changes in the code since then, but the general principles remain the same.) Patches 14, 15 and 16 add the support for memory-transaction-aware IOMMUs. The general approach is that we have the concept of an IOMMU index (similar to the TCG MMU index), which selects which of multiple possible translation tables in the IOMMU we're trying to use. Most IOMMUs will support just a single index. When you register an IOMMU notifier and when you call the translate method you have to specify which IOMMU index you want. There's a method for getting the index that applies for a particular set of transaction attributes. All the current IOMMU implementations have just one iommu index, and all the current users of the notify API assume that. Patch 17 adds the support for TCG execution from memory that sits behind an IOMMU. We do this in a fairly simple way on the assumption that changes to the IOMMU config at runtime will be fairly uncommon: we just flush the CPU TLB so it forgets about any cached results when we get an IOMMU unmap notification. (This is similar to how we handle reconfigurations of the memory map done by mapping or unmapping MemoryRegions.) NB: I'm not completely sure that calling tlb_flush() here is sufficient to be non-racy in the case where CPU A has triggered the IOMMU unmap notify by changing the IOMMU config while CPU B is executing from memory behind the IOMMU, but tlb_flush() is what tcg_commit() uses so I guess it's OK. I think the idea here is that any delay in flushing B's TLB is just equivalent to B having executed a little bit further before A got to changing the config? Patches 18-21 implement the TrustZone Memory Protection Controller, which is a fairly simple piece of hardware that just configurably either allows or blocks transactions depending on attrs.secure. Patches 22 and 23 deal with a limitation in our or-irq device, which currently only allows 16 input lines (we need 17 for one of the OR gates in the IoTKit object). The patches raise the limit to 32, but in a way that means we can easily raise it further in future without migration compatibility problems. Patches 24-27 add MPCs to the IoTKit SoC object and to the mps2-an505 board model, and wire them up appropriately. Based-on: 20180518153157.14899-1-peter.maydell@linaro.org [MAINTAINERS: Add entries for newer MPS2 boards and devices] purely to avoid the textual conflict when we add MAINTAINERS entries Peter Maydell (27): memory.h: Improve IOMMU related documentation Make tb_invalidate_phys_addr() take a MemTxAttrs argument Make address_space_translate{,_cached}() take a MemTxAttrs argument Make address_space_map() take a MemTxAttrs argument Make address_space_access_valid() take a MemTxAttrs argument Make flatview_extend_translation() take a MemTxAttrs argument Make memory_region_access_valid() take a MemTxAttrs argument Make MemoryRegion valid.accepts callback take a MemTxAttrs argument Make flatview_access_valid() take a MemTxAttrs argument Make flatview_translate() take a MemTxAttrs argument Make address_space_get_iotlb_entry() take a MemTxAttrs argument Make flatview_do_translate() take a MemTxAttrs argument Make address_space_translate_iommu take a MemTxAttrs argument iommu: Add IOMMU index concept to IOMMU API iommu: Add IOMMU index argument to notifier APIs iommu: Add IOMMU index argument to translate method exec.c: Handle IOMMUs in address_space_translate_for_iotlb() hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller hw/misc/tz-mpc.c: Implement registers hw/misc/tz-mpc.c: Implement correct blocked-access behaviour hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY hw/core/or-irq: Support more than 16 inputs to an OR gate hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS hw/arm/iotkit: Instantiate MPC hw/arm/iotkit: Wire up MPC interrupt lines hw/arm/mps2-tz.c: Instantiate MPCs hw/misc/Makefile.objs | 1 + include/exec/exec-all.h | 8 +- include/exec/memory-internal.h | 3 +- include/exec/memory.h | 194 ++++++++-- include/hw/arm/iotkit.h | 8 + include/hw/misc/iotkit-secctl.h | 8 + include/hw/misc/tz-mpc.h | 80 +++++ include/hw/or-irq.h | 5 +- include/migration/vmstate.h | 3 + include/qom/cpu.h | 3 + include/sysemu/dma.h | 6 +- accel/tcg/cputlb.c | 3 +- accel/tcg/translate-all.c | 4 +- exec.c | 254 +++++++++++--- hw/alpha/typhoon.c | 3 +- hw/arm/iotkit.c | 112 +++++- hw/arm/mps2-tz.c | 71 ++-- hw/arm/smmuv3.c | 2 +- hw/core/or-irq.c | 39 ++- hw/dma/rc4030.c | 2 +- hw/hppa/dino.c | 3 +- hw/i386/amd_iommu.c | 2 +- hw/i386/intel_iommu.c | 6 +- hw/misc/iotkit-secctl.c | 38 +- hw/misc/tz-mpc.c | 604 ++++++++++++++++++++++++++++++++ hw/nvram/fw_cfg.c | 12 +- hw/ppc/spapr_iommu.c | 5 +- hw/s390x/s390-pci-bus.c | 2 +- hw/s390x/s390-pci-inst.c | 7 +- hw/scsi/esp.c | 3 +- hw/sparc/sun4m_iommu.c | 3 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/vfio/common.c | 9 +- hw/virtio/vhost.c | 10 +- hw/xen/xen_pt_msi.c | 3 +- memory.c | 45 ++- memory_ldst.inc.c | 18 +- target/ppc/mmu-hash64.c | 3 +- target/riscv/helper.c | 2 +- target/s390x/diag.c | 6 +- target/s390x/excp_helper.c | 3 +- target/s390x/mmu_helper.c | 3 +- target/s390x/sigp.c | 3 +- target/xtensa/op_helper.c | 3 +- MAINTAINERS | 2 + default-configs/arm-softmmu.mak | 1 + hw/misc/trace-events | 8 + 47 files changed, 1452 insertions(+), 163 deletions(-) create mode 100644 include/hw/misc/tz-mpc.h create mode 100644 hw/misc/tz-mpc.c -- 2.17.0