Message ID | 20180604152941.20374-1-peter.maydell@linaro.org |
---|---|
Headers | show |
Series | iommu: support txattrs, support TCG execution, implement TZ MPC | expand |
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180604152941.20374-1-peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH v2 00/13] iommu: support txattrs, support TCG execution, implement TZ MPC === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 3b4bfa3eff hw/arm/mps2-tz.c: Instantiate MPCs c2790822f9 hw/arm/iotkit: Wire up MPC interrupt lines 9746b202df hw/arm/iotkit: Instantiate MPC 4d48d06522 hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS 5e08d07dc5 hw/core/or-irq: Support more than 16 inputs to an OR gate dff0cc68f1 hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate cc42636d7c hw/misc/tz-mpc.c: Implement correct blocked-access behaviour 57b4be59f6 hw/misc/tz-mpc.c: Implement registers cb3c936f45 hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller 7d9ec3d9dd exec.c: Handle IOMMUs in address_space_translate_for_iotlb() 3c592827bc iommu: Add IOMMU index argument to translate method ca96fcdcf6 iommu: Add IOMMU index argument to notifier APIs 85bade9641 iommu: Add IOMMU index concept to IOMMU API === OUTPUT BEGIN === Checking PATCH 1/13: iommu: Add IOMMU index concept to IOMMU API... Checking PATCH 2/13: iommu: Add IOMMU index argument to notifier APIs... Checking PATCH 3/13: iommu: Add IOMMU index argument to translate method... Checking PATCH 4/13: exec.c: Handle IOMMUs in address_space_translate_for_iotlb()... Checking PATCH 5/13: hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller... WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #84: new file mode 100644 total: 0 errors, 1 warnings, 486 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 6/13: hw/misc/tz-mpc.c: Implement registers... Checking PATCH 7/13: hw/misc/tz-mpc.c: Implement correct blocked-access behaviour... Checking PATCH 8/13: hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate... Checking PATCH 9/13: hw/core/or-irq: Support more than 16 inputs to an OR gate... ERROR: spaces required around that '*' (ctx:VxV) #70: FILE: hw/core/or-irq.c:108: + .subsections = (const VMStateDescription*[]) { ^ total: 1 errors, 0 warnings, 62 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 10/13: hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS... ERROR: spaces required around that '*' (ctx:VxV) #91: FILE: hw/misc/iotkit-secctl.c:711: + .subsections = (const VMStateDescription*[]) { ^ total: 1 errors, 0 warnings, 100 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 11/13: hw/arm/iotkit: Instantiate MPC... Checking PATCH 12/13: hw/arm/iotkit: Wire up MPC interrupt lines... Checking PATCH 13/13: hw/arm/mps2-tz.c: Instantiate MPCs... === OUTPUT END === Test command exited with code: 1 --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
On Mon, Jun 04, 2018 at 04:29:28PM +0100, Peter Maydell wrote: > Hi; this is v2 of my iommu patchset, which does: > * support IOMMUs that are aware of memory transaction attributes and > may generate different translations for different attributes > * support TCG execution out of memory which is behind an IOMMU > * implement the Arm TrustZone Memory Protection Controller > (which needs both the above features in the IOMMU core code) > * use the MPC in the mps2-an505 board > > Patches 1-3 add the support for memory-transaction-aware > IOMMUs. The general approach is that we have the concept of an > IOMMU index (similar to the TCG MMU index), which selects which of > multiple possible translation tables in the IOMMU we're trying to use. > Most IOMMUs will support just a single index. When you register an > IOMMU notifier and when you call the translate method you have to > specify which IOMMU index you want. There's a method for getting the > index that applies for a particular set of transaction attributes. > All the current IOMMU implementations have just one iommu index, and > all the current users of the notify API assume that. Hi, Peter, It seems that this series is still using the IOMMU index way. In case I missed anything... Could you elaborate a bit on why this IOMMU index solution is preferred comparing to the way to pass in MemTxAttrs? Or was there any further discussion I missed on the topic? My last post to previous series is here: https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05702.html In that, I was still confused on why we couldn't use the existing MemTxAttrs directly instead of the new IOMMU index (and I explained on why that was prefered at least to me). I didn't see replies afterwards. Frankly speaking I fully trust the expertise of you and all the reviewers. I am just afraid I missed any context along the way. Thanks, -- Peter Xu
On 5 June 2018 at 08:39, Peter Xu <peterx@redhat.com> wrote: > On Mon, Jun 04, 2018 at 04:29:28PM +0100, Peter Maydell wrote: >> Hi; this is v2 of my iommu patchset, which does: >> * support IOMMUs that are aware of memory transaction attributes and >> may generate different translations for different attributes >> * support TCG execution out of memory which is behind an IOMMU >> * implement the Arm TrustZone Memory Protection Controller >> (which needs both the above features in the IOMMU core code) >> * use the MPC in the mps2-an505 board > It seems that this series is still using the IOMMU index way. In case > I missed anything... Could you elaborate a bit on why this IOMMU index > solution is preferred comparing to the way to pass in MemTxAttrs? Or > was there any further discussion I missed on the topic? > > My last post to previous series is here: > > https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05702.html > > In that, I was still confused on why we couldn't use the existing > MemTxAttrs directly instead of the new IOMMU index (and I explained on > why that was prefered at least to me). I didn't see replies > afterwards. Broadly speaking I didn't think I had any further better explanation than I'd already given in that thread, eg here: https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05250.html and here: https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05513.html If you want to make a specific (detailed) counterproposal of a different API, I'm happy to look at whether that works for the use cases I care about and whether it's a nicer way to do it. thanks -- PMM
On Tue, Jun 05, 2018 at 10:13:12AM +0100, Peter Maydell wrote: > On 5 June 2018 at 08:39, Peter Xu <peterx@redhat.com> wrote: > > On Mon, Jun 04, 2018 at 04:29:28PM +0100, Peter Maydell wrote: > >> Hi; this is v2 of my iommu patchset, which does: > >> * support IOMMUs that are aware of memory transaction attributes and > >> may generate different translations for different attributes > >> * support TCG execution out of memory which is behind an IOMMU > >> * implement the Arm TrustZone Memory Protection Controller > >> (which needs both the above features in the IOMMU core code) > >> * use the MPC in the mps2-an505 board > > > It seems that this series is still using the IOMMU index way. In case > > I missed anything... Could you elaborate a bit on why this IOMMU index > > solution is preferred comparing to the way to pass in MemTxAttrs? Or > > was there any further discussion I missed on the topic? > > > > My last post to previous series is here: > > > > https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05702.html > > > > In that, I was still confused on why we couldn't use the existing > > MemTxAttrs directly instead of the new IOMMU index (and I explained on > > why that was prefered at least to me). I didn't see replies > > afterwards. > > Broadly speaking I didn't think I had any further better > explanation than I'd already given in that thread, eg here: > https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05250.html > and here: > https://lists.gnu.org/archive/html/qemu-devel/2018-05/msg05513.html > > If you want to make a specific (detailed) counterproposal of a > different API, I'm happy to look at whether that works for > the use cases I care about and whether it's a nicer way to do it. I posted a few pesudo code (ok, it can actually compile...) to show what I meant. Please have a look there: [RFC 0/3] memory: enhance IOMMU notifier to support USER bit I very suspect I missed some important requirement there but I cannot really figure it out myself. Hope these patches can either provide an alternative solution on the problem, or help me to figure out what I missed. Thanks, -- Peter Xu
On 4 June 2018 at 16:29, Peter Maydell <peter.maydell@linaro.org> wrote: > Hi; this is v2 of my iommu patchset, which does: > * support IOMMUs that are aware of memory transaction attributes and > may generate different translations for different attributes > * support TCG execution out of memory which is behind an IOMMU > * implement the Arm TrustZone Memory Protection Controller > (which needs both the above features in the IOMMU core code) > * use the MPC in the mps2-an505 board > Unreviewed patches: 4, 6, 7, 8, 9, 10 Ping for further reviews, comments, etc, please. I'd like to put this in via target-arm.next in the not too distant future. thanks -- PMM
On 14 June 2018 at 17:51, Peter Maydell <peter.maydell@linaro.org> wrote: > On 4 June 2018 at 16:29, Peter Maydell <peter.maydell@linaro.org> wrote: >> Hi; this is v2 of my iommu patchset, which does: >> * support IOMMUs that are aware of memory transaction attributes and >> may generate different translations for different attributes >> * support TCG execution out of memory which is behind an IOMMU >> * implement the Arm TrustZone Memory Protection Controller >> (which needs both the above features in the IOMMU core code) >> * use the MPC in the mps2-an505 board > >> Unreviewed patches: 4, 6, 7, 8, 9, 10 > > Ping for further reviews, comments, etc, please. I'd like > to put this in via target-arm.next in the not too distant > future. Thanks for the reviews; since 1-5 and 9 have been reviewed and have no issues, I'm going to put those into target-arm.next (to reduce the size of v3 of this series and avoid possible issues with conflicts with other iommu related patchsets). thanks -- PMM