From patchwork Fri Aug 31 13:26:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 145609 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp783069ljw; Fri, 31 Aug 2018 06:27:24 -0700 (PDT) X-Google-Smtp-Source: ANB0VdajD89TKONlsEoBBUg2Z8+j5UnXuTX+A4wKEUBhivu9j44byTiXgc3Nhlew1znZoRe9HUEg X-Received: by 2002:a63:ad44:: with SMTP id y4-v6mr14197838pgo.138.1535722044731; Fri, 31 Aug 2018 06:27:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535722044; cv=none; d=google.com; s=arc-20160816; b=KUN3E4UEVOV6LqUItF6Vqjnai+YfngQhAr+qgk4J7evJBsU9iFtnvMQs8RN4xOjMEW BD9cBLLYqQu3cjkCVcg26ZIDuGVMghPEWdUdleLExNYAdb8X/ox+4IikZGAo/4KDlXn2 DEgYgQ/AQCnMjzTbjueub3gL8VRsv6w4VrhxCoTkdIIq6/6H45+y9fzQrVhcAQIuV7+t YJrITiW3gzFG09ex3FYWahwwx/3n2cPEeSmpFo2bCQSpP3nMYTm757oovhoE9irfrEWN 6FnTb7aS5grLeuYORhM6e/d7/43O7OVRmCIUw5ZZQ2WAjK0Xieut66NM0bmARhAQ9WbD swoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=Frvffngsq1LUwp1FDPgVE8dy48uCkegvBnyinckaiPU=; b=cITfraeF3dQ/VpQyIetjpJK47RCV8W16vucFLbHp3rKhUc/mnVEM6I52Yurn5dtXep UGrnWWMz9hkSsvKZ/kV3mXKCg7O1m3B+JEc36cocCDG3KiSlmsi86DMk0WCQLWGZImcC hxESC7L4JgEnGNqtRhTJAeQhLi8bWesu+xevZ/3DCeXLyFsXqcmp6GRVVam3OQRtwBvu wmmybGi9uF2Sb+8Vbi9dzAqns3P6l++x4FJHzhAGhcDWQbH/L9n+MKErVL0tOWjADiX3 vBSTk+nIKOTIBnMHlC1xhQGnePS/zL3Fb3yQVaI2XnMtzAWkqIAArn/SH38r69WMat7a EV2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hNAMA9K+; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 444542110BD45 for ; Fri, 31 Aug 2018 06:27:21 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id f6-v6so5500204plo.1 for ; Fri, 31 Aug 2018 06:27:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=fJPfvmSZoM60sMQBff7mnfSLOwq/YZ/XItGhYnqGgxs=; b=hNAMA9K+qGY+bxFQ8ljG2DSlJtwctvk6ZJYAbLL8nt+oJu8gZQ4SHF8Zqo3KfonsmR zAawBzKzI1/lyiythM2MYgmSwi2uKE76YH8Q4FbAC1j+NZy503yVstAWjlogPanYo1Rs BQfnzy7byxLD36R+xEB4gfYeA3n/nY5epkF6U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; 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2 Unify some D0x modules; Change since v4: 1 build on every commit: Squash "Add PciPlatformLib" to "Add several base file for D06"; Reorder OemMiscLibD06 before "Add edk2-non-osi components for D06"; Move some mudules after "Add edk2-non-osi components for D06"; Move gOemConfigGuid to "Stop watchdog"; 2 Delete needless SnpDxe; 3 Reorder "Unify HisiAcpiPlatformDxe"; 4 Modify Signed-off-by and add Reviewed-by; 5 Modify other comments in v4; Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: d06-platform-v5 Heyi Guo (3): Hisilicon/D06: Add Debug Serial Port Init Driver Hisilicon/Hi1620: Add ACPI PPTT table Platform/Hisilicon/D06: Enable ACPI PPTT Luqi Jiang (1): Hisilicon/D06: add apei driver Ming Huang (19): Hisilicon/D0x: Modify PcdBootManagerMenuFile for build Silicon/Hisilicon/Acpi: Unify HisiAcpiPlatformDxe Hisilicon/D06: Add several base file for D06 Platform/Hisilicon/D06: Add M41T83RealTimeClockLib Hisilicon/D06: Add OemMiscLibD06 Platform/Hisilicon/D06: Add edk2-non-osi components for D06 Hisilicon/D06: Add some modules Silicon/Hisilicon/D06: Wait for all disk ready Hisilicon/D06: Add ACPI Tables for D06 Silicon/Hisilicon/D06: Stop watchdog Platform/Hisilicon/D06: Add OemNicLib Platform/Hisilicon/D06: Add OemNicConfig2P Driver Platform/Hisilicon/D06: Add EarlyConfigPeim peim Platform/Hisilicon/D06: Add PciHostBridgeLib Platform/Hisilicon/D06: Add capsule upgrade support Silicon/Hisilicon: Add I2C Bus Exception handle function Silicon/Hisilicon/Setup: Support SPCR table switch Silicon/Hisilicon/setup: Enable/disable SMMU Platform/Hisilicon/D0x: Update version string to 18.08 Sun Yuanchen (2): Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h Hisilicon/D0x: Update SMBIOS type9 info Yang XinYi (2): Hisilicon/D06: Add Hi1620OemConfigUiLib Silicon/Hisilicon/Hi1620/Setup: Add Setup Item "EnableGOP" ZhenYao (1): Silicon/Hisilicon: Modify for disable slave core clock. Platform/Hisilicon/D06/D06.dec | 29 + Silicon/Hisilicon/Hi1620/Hi1620.dec | 23 + Silicon/Hisilicon/HisiPkg.dec | 1 + Platform/Hisilicon/D03/D03.dsc | 4 +- Platform/Hisilicon/D05/D05.dsc | 4 +- Platform/Hisilicon/D06/D06.dsc | 489 ++++ Platform/Hisilicon/D06/D06.fdf | 441 ++++ .../OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 + .../Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + .../OemNicConfig2PHi1620/OemNicConfig2P.inf | 43 + .../SystemFirmwareDescriptor.inf | 50 + .../EarlyConfigPeim/EarlyConfigPeimD06.inf | 50 + .../Library/OemMiscLibD06/OemMiscLibD06.inf | 50 + .../D06/Library/OemNicLib/OemNicLib.inf | 35 + .../PciHostBridgeLib/PciHostBridgeLib.inf | 36 + .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 3 +- .../Hisilicon/Hi1620/Drivers/Apei/Apei.inf | 59 + .../Pl011DebugSerialPortInitDxe.inf | 48 + .../Hi1620AcpiTables/AcpiTablesHi1620.inf | 60 + .../Hi1620OemConfigUiLib/OemConfigUiLib.inf | 68 + .../Hi1620PciPlatformLib.inf | 30 + Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf | 48 + .../M41T83RealTimeClockLib.inf | 46 + .../PlatformBootManagerLib.inf | 5 + .../OemNicConfig2PHi1620/OemNicConfig.h | 25 + .../Hisilicon/D06/Include/Library/CpldD06.h | 39 + .../Hisilicon/Hi1610/Include/PlatformArch.h | 15 +- .../Hisilicon/Hi1616/Include/PlatformArch.h | 12 + Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h | 41 + .../Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h | 43 + .../Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h | 146 ++ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.h | 110 + .../Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h | 140 ++ .../Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h | 59 + .../Hi1620/Drivers/Apei/OemApeiHi1620.h | 43 + .../Hi1620/Hi1620AcpiTables/Hi1620Platform.h | 27 + .../Hi1620/Hi1620OemConfigUiLib/OemConfig.h | 142 ++ .../Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h | 64 + .../Hi1620/Include/Library/SerdesLib.h | 85 + .../Hisilicon/Hi1620/Include/PlatformArch.h | 67 + Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 68 + .../Hisilicon/Include/Library/AcpiNextLib.h | 31 +- .../Hisilicon/Include/Library/IpmiCmdLib.h | 16 + .../Include/Library/OemAddressMapLib.h | 8 + .../Hisilicon/Include/Library/OemConfigData.h | 84 + .../Hisilicon/Include/Library/OemMiscLib.h | 7 +- Silicon/Hisilicon/Include/Library/OemNicLib.h | 57 + .../Include/Library/PlatformSysCtrlLib.h | 6 + .../M41T83RealTimeClock.h | 158 ++ .../Hi1620OemConfigUiLib/OemConfigVfr.vfr | 89 + .../Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 32 + .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +- .../OemNicConfig2PHi1620/OemNicConfig2P.c | 71 + .../SystemFirmwareDescriptorPei.c | 70 + .../D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 107 + .../Library/OemMiscLibD06/BoardFeatureD06.c | 432 ++++ .../D06/Library/OemMiscLibD06/OemMiscLibD06.c | 209 ++ .../D06/Library/OemNicLib/OemNicLib.c | 569 +++++ .../PciHostBridgeLib/PciHostBridgeLib.c | 635 ++++++ .../HisiAcpiPlatformDxe/UpdateAcpiTable.c | 91 +- .../Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +- Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c | 108 + .../Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c | 91 + .../Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c | 349 +++ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.c | 330 +++ .../Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c | 374 ++++ .../Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c | 118 + .../Hi1620/Drivers/Apei/OemApeiHi1620.c | 337 +++ .../Pl011DebugSerialPortInitDxe.c | 64 + .../Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 363 +++ .../Hi1620PciPlatformLib.c | 67 + Silicon/Hisilicon/Hi1620/Pptt/Pptt.c | 543 +++++ .../M41T83RealTimeClockLib.c | 559 +++++ .../PlatformBootManagerLib/PlatformBm.c | 59 + .../SystemFirmwareUpdateConfig.ini | 46 + .../SystemFirmwareDescriptor.aslc | 81 + .../OemMiscLibD06/BoardFeatureD06Strings.uni | 66 + .../Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl | 409 ++++ .../Hi1620/Hi1620AcpiTables/Dsdt/Com.asl | 30 + .../Hi1620AcpiTables/Dsdt/DsdtHi1620.asl | 35 + .../Hi1620AcpiTables/Dsdt/Hi1620Apei.asl | 93 + .../Hi1620AcpiTables/Dsdt/Hi1620Ged.asl | 58 + .../Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl | 1459 ++++++++++++ .../Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl | 41 + .../Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 1216 ++++++++++ .../Hi1620AcpiTables/Dsdt/Hi1620Power.asl | 28 + .../Hi1620AcpiTables/Dsdt/Hi1620Rde.asl | 47 + .../Hi1620AcpiTables/Dsdt/Hi1620Sec.asl | 57 + .../Dsdt/Hi1620Socip4_i2c100k.asl | 249 +++ .../Dsdt/Hi1620Socip4_i2c400k.asl | 249 +++ .../Hi1620AcpiTables/Dsdt/LpcUart_clk.asl | 49 + .../Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl | 1658 ++++++++++++++ .../Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl | 49 + .../Hi1620/Hi1620AcpiTables/Facs.aslc | 67 + .../Hi1620/Hi1620AcpiTables/Fadt.aslc | 91 + .../Hi1620/Hi1620AcpiTables/Gtdt.aslc | 86 + .../Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc | 86 + .../Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 1989 +++++++++++++++++ .../Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 1736 ++++++++++++++ .../Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc | 64 + .../Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc | 64 + .../Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc | 81 + .../Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc | 166 ++ .../Hi1620/Hi1620AcpiTables/MadtHi1620.aslc | 375 ++++ .../Hi1620OemConfigUiLib/MemoryConfig.hfr | 154 ++ .../Hi1620OemConfigUiLib/MemoryConfig.uni | 103 + .../Hi1620OemConfigUiLib/MiscConfig.hfr | 41 + .../Hi1620OemConfigUiLib/MiscConfig.uni | 27 + .../Hi1620OemConfigUiLib/OemConfigUiLib.uni | 24 + .../OemConfigUiLibStrings.uni | 42 + .../Hi1620OemConfigUiLib/PcieConfig.hfr | 219 ++ .../PcieConfigStrings.uni | 111 + .../Hi1620OemConfigUiLib/PciePortConfig.hfr | 167 ++ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr | 172 ++ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.uni | 85 + .../Hi1620OemConfigUiLib/iBMCConfig.hfr | 81 + .../Hi1620OemConfigUiLib/iBMCConfig.uni | 34 + 117 files changed, 20778 insertions(+), 32 deletions(-) create mode 100644 Platform/Hisilicon/D06/D06.dec create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620.dec create mode 100644 Platform/Hisilicon/D06/D06.dsc create mode 100644 Platform/Hisilicon/D06/D06.fdf create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h create mode 100644 Platform/Hisilicon/D06/Include/Library/CpldD06.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h create mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h create mode 100644 Silicon/Hisilicon/Hi1620/Include/PlatformArch.h create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.h create mode 100644 Silicon/Hisilicon/Include/Library/OemConfigData.h create mode 100644 Silicon/Hisilicon/Include/Library/OemNicLib.h create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.c create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c create mode 100644 Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni -- 2.18.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm