| Message ID | 20181108135352.8459-1-jbrunet@baylibre.com |
|---|---|
| Headers | show |
| Series | arm64: dts: meson-axg: enable SCPI | expand |
On 08/11/2018 14:53, Jerome Brunet wrote: > MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113. > These mailboxes are needed for SCPI > > Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support") > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index 3cc0044d3468..ff8b3406aff6 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -1067,9 +1067,9 @@ > }; > }; > > - mailbox: mailbox@ff63dc00 { > + mailbox: mailbox@ff63c404 { > compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; > - reg = <0 0xff63dc00 0 0x400>; > + reg = <0 0xff63c404 0 0x4c>; > interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, > <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, > <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
On 08/11/2018 14:53, Jerome Brunet wrote: > Correct the unit-address in the node name of the SRAM shared memory > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index ff8b3406aff6..b8893675e39c 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -1659,12 +1659,12 @@ > #size-cells = <1>; > ranges = <0 0x0 0xfffc0000 0x20000>; > > - cpu_scp_lpri: scp-shmem@0 { > + cpu_scp_lpri: scp-shmem@13000 { > compatible = "amlogic,meson-axg-scp-shmem"; > reg = <0x13000 0x400>; > }; > > - cpu_scp_hpri: scp-shmem@200 { > + cpu_scp_hpri: scp-shmem@13400 { > compatible = "amlogic,meson-axg-scp-shmem"; > reg = <0x13400 0x400>; > }; > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
On 08/11/2018 14:53, Jerome Brunet wrote: > Enable SCPI on the axg platform, with cpu clock and hwmon > (core temperature) support > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index b8893675e39c..5f512c91471e 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -79,6 +79,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > next-level-cache = <&l2>; > + clocks = <&scpi_dvfs 0>; > }; > > cpu1: cpu@1 { > @@ -87,6 +88,7 @@ > reg = <0x0 0x1>; > enable-method = "psci"; > next-level-cache = <&l2>; > + clocks = <&scpi_dvfs 0>; > }; > > cpu2: cpu@2 { > @@ -95,6 +97,7 @@ > reg = <0x0 0x2>; > enable-method = "psci"; > next-level-cache = <&l2>; > + clocks = <&scpi_dvfs 0>; > }; > > cpu3: cpu@3 { > @@ -103,6 +106,7 @@ > reg = <0x0 0x3>; > enable-method = "psci"; > next-level-cache = <&l2>; > + clocks = <&scpi_dvfs 0>; > }; > > l2: l2-cache0 { > @@ -137,6 +141,28 @@ > }; > }; > > + scpi { > + compatible = "arm,scpi-pre-1.0"; > + mboxes = <&mailbox 1 &mailbox 2>; > + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; > + > + scpi_clocks: clocks { > + compatible = "arm,scpi-clocks"; > + > + scpi_dvfs: clock-controller { > + compatible = "arm,scpi-dvfs-clocks"; > + #clock-cells = <1>; > + clock-indices = <0>; > + clock-output-names = "vcpu"; > + }; > + }; > + > + scpi_sensors: sensors { > + compatible = "amlogic,meson-gxbb-scpi-sensors"; > + #thermal-sensor-cells = <1>; > + }; > + }; > + > soc { > compatible = "simple-bus"; > #address-cells = <2>; > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>