mbox series

[0/6] Implement asm flag outputs for arm + aarch64

Message ID 20191108105408.27584-1-richard.henderson@linaro.org
Headers show
Series Implement asm flag outputs for arm + aarch64 | expand

Message

Richard Henderson Nov. 8, 2019, 10:54 a.m. UTC 
I've put the implementation into config/arm/aarch-common.c, so
that it can be shared between the two targets.  This required
a little bit of cleanup to the CC modes and constraints to get
the two targets to match up.

I really should have done more than just x86 years ago, so that
it would be done now and I could just use it in the kernel...  ;-)


r~


Richard Henderson (6):
  aarch64: Add "c" constraint
  arm: Fix the "c" constraint
  arm: Rename CC_NOOVmode to CC_NZmode
  arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__
  arm: Add testsuite checks for asm-flag
  aarch64: Add testsuite checks for asm-flag

 gcc/config/arm/aarch-common-protos.h          |   6 +
 gcc/config/aarch64/aarch64-c.c                |   2 +
 gcc/config/aarch64/aarch64.c                  |   3 +
 gcc/config/arm/aarch-common.c                 | 131 ++++++++++++
 gcc/config/arm/arm-c.c                        |   1 +
 gcc/config/arm/arm.c                          |  15 +-
 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c |  34 ++++
 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c |  36 ++++
 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c |  30 +++
 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c |  43 ++++
 gcc/testsuite/gcc.target/arm/asm-flag-1.c     |  35 ++++
 gcc/testsuite/gcc.target/arm/asm-flag-3.c     |  36 ++++
 gcc/testsuite/gcc.target/arm/asm-flag-5.c     |  30 +++
 gcc/testsuite/gcc.target/arm/asm-flag-6.c     |  43 ++++
 gcc/config/aarch64/constraints.md             |   4 +
 gcc/config/arm/arm-modes.def                  |   4 +-
 gcc/config/arm/arm.md                         | 186 +++++++++---------
 gcc/config/arm/constraints.md                 |   5 +-
 gcc/config/arm/predicates.md                  |   2 +-
 gcc/config/arm/thumb1.md                      |   8 +-
 gcc/config/arm/thumb2.md                      |  34 ++--
 gcc/doc/extend.texi                           |  33 ++++
 22 files changed, 596 insertions(+), 125 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c

-- 
2.17.1

Comments

Richard Sandiford Nov. 12, 2019, 8:21 p.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:
> I've put the implementation into config/arm/aarch-common.c, so

> that it can be shared between the two targets.  This required

> a little bit of cleanup to the CC modes and constraints to get

> the two targets to match up.

>

> I really should have done more than just x86 years ago, so that

> it would be done now and I could just use it in the kernel...  ;-)


Thanks for doing this, looks great.

Apart from the vc/vs thing you mentioned in the follow-up for 4/6,
it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo".  OK for
aarch64 with those added.

Richard
Richard Henderson Nov. 13, 2019, 8:06 a.m. UTC | #2 
On 11/12/19 9:21 PM, Richard Sandiford wrote:
> Apart from the vc/vs thing you mentioned in the follow-up for 4/6,

> it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo".  OK for

> aarch64 with those added.


Are those aliases for two of the other conditions?  They're not in the list
within the pseudocode for ConditionHolds in the ARM ARM.  Which is what I was
documenting to support...


r~
Richard Sandiford Nov. 13, 2019, 8:32 a.m. UTC | #3 
Richard Henderson <richard.henderson@linaro.org> writes:
> On 11/12/19 9:21 PM, Richard Sandiford wrote:

>> Apart from the vc/vs thing you mentioned in the follow-up for 4/6,

>> it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo".  OK for

>> aarch64 with those added.

>

> Are those aliases for two of the other conditions?  They're not in the list

> within the pseudocode for ConditionHolds in the ARM ARM.  Which is what I was

> documenting to support...


Yeah, hs==cs and lo==cc.  But I think they're commonly used, and are the
natural choice if you're testing the result of an unsigned comparison.

Richard