[v9,00/46] target/arm: Implement ARMv8.5-MemTag, system mode

Message ID 20200626033144.790098-1-richard.henderson@linaro.org
Headers show
Series
  • target/arm: Implement ARMv8.5-MemTag, system mode
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Message

Richard Henderson June 26, 2020, 3:30 a.m.
Version 9 incorporates some review:

  * Adjust some commentary.
  * Added an assert for tbi in aarch64_tr_init_disas_context
  * Split arm,armv8.5-memtag to a new, final, patch.  We might
    just leave this one out of qemu mainline until the kernel
    patch set that requires it gets merged.


r~


Richard Henderson (46):
  target/arm: Add isar tests for mte
  target/arm: Improve masking of SCR RES0 bits
  target/arm: Add support for MTE to SCTLR_ELx
  target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
  target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
  target/arm: Add DISAS_UPDATE_NOCHAIN
  target/arm: Add MTE system registers
  target/arm: Add MTE bits to tb_flags
  target/arm: Implement the IRG instruction
  target/arm: Revise decoding for disas_add_sub_imm
  target/arm: Implement the ADDG, SUBG instructions
  target/arm: Implement the GMI instruction
  target/arm: Implement the SUBP instruction
  target/arm: Define arm_cpu_do_unaligned_access for user-only
  target/arm: Implement LDG, STG, ST2G instructions
  target/arm: Implement the STGP instruction
  target/arm: Restrict the values of DCZID.BS under TCG
  target/arm: Simplify DC_ZVA
  target/arm: Implement the LDGM, STGM, STZGM instructions
  target/arm: Implement the access tag cache flushes
  target/arm: Move regime_el to internals.h
  target/arm: Move regime_tcr to internals.h
  target/arm: Add gen_mte_check1
  target/arm: Add gen_mte_checkN
  target/arm: Implement helper_mte_check1
  target/arm: Implement helper_mte_checkN
  target/arm: Add helper_mte_check_zva
  target/arm: Use mte_checkN for sve unpredicated loads
  target/arm: Use mte_checkN for sve unpredicated stores
  target/arm: Use mte_check1 for sve LD1R
  target/arm: Tidy trans_LD1R_zpri
  target/arm: Add arm_tlb_bti_gp
  target/arm: Add mte helpers for sve scalar + int loads
  target/arm: Add mte helpers for sve scalar + int stores
  target/arm: Add mte helpers for sve scalar + int ff/nf loads
  target/arm: Handle TBI for sve scalar + int memory ops
  target/arm: Add mte helpers for sve scatter/gather memory ops
  target/arm: Complete TBI clearing for user-only for SVE
  target/arm: Implement data cache set allocation tags
  target/arm: Set PSTATE.TCO on exception entry
  target/arm: Always pass cacheattr to get_phys_addr
  target/arm: Cache the Tagged bit for a page in MemTxAttrs
  target/arm: Create tagged ram when MTE is enabled
  target/arm: Add allocation tag storage for system mode
  target/arm: Enable MTE
  target/arm: Add arm,armv8.5-memtag to dtb

 include/hw/arm/boot.h          |    3 +
 target/arm/cpu.h               |   50 +-
 target/arm/helper-a64.h        |   16 +
 target/arm/helper-sve.h        |  488 ++++++++++++
 target/arm/helper.h            |    2 +
 target/arm/internals.h         |  153 +++-
 target/arm/translate-a64.h     |    5 +
 target/arm/translate.h         |   23 +-
 hw/arm/boot.c                  |   12 +-
 hw/arm/virt.c                  |   57 +-
 target/arm/cpu.c               |   81 +-
 target/arm/cpu64.c             |    5 +
 target/arm/helper-a64.c        |   94 +--
 target/arm/helper.c            |  423 +++++++---
 target/arm/m_helper.c          |   11 +-
 target/arm/mte_helper.c        |  906 +++++++++++++++++++++
 target/arm/op_helper.c         |   16 +
 target/arm/sve_helper.c        |  616 +++++++++++---
 target/arm/tlb_helper.c        |   13 +-
 target/arm/translate-a64.c     |  657 +++++++++++++--
 target/arm/translate-sve.c     | 1366 +++++++++++++++++++++-----------
 target/arm/translate-vfp.inc.c |    4 +-
 target/arm/translate.c         |   16 +-
 target/arm/Makefile.objs       |    1 +
 24 files changed, 4182 insertions(+), 836 deletions(-)
 create mode 100644 target/arm/mte_helper.c

-- 
2.25.1

Comments

Richard Henderson June 26, 2020, 3:35 a.m. | #1
On 6/25/20 8:30 PM, Richard Henderson wrote:
> Version 9 incorporates some review:

> 

>   * Adjust some commentary.

>   * Added an assert for tbi in aarch64_tr_init_disas_context

>   * Split arm,armv8.5-memtag to a new, final, patch.  We might

>     just leave this one out of qemu mainline until the kernel

>     patch set that requires it gets merged.


Meant to say, the following patches lack review:

43-target-arm-Create-tagged-ram-when-MTE-is-enabled.patch
44-target-arm-Add-allocation-tag-storage-for-system-.patch
46-target-arm-Add-arm-armv8.5-memtag-to-dtb.patch

That last one of course is new.


r~
no-reply@patchew.org June 26, 2020, 4:50 a.m. | #2
Patchew URL: https://patchew.org/QEMU/20200626033144.790098-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200626033144.790098-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20200626033144.790098-1-richard.henderson@linaro.org -> patchew/20200626033144.790098-1-richard.henderson@linaro.org
Switched to a new branch 'test'
19fd148 target/arm: Add arm,armv8.5-memtag to dtb
68e0e2c target/arm: Enable MTE
fd1e477 target/arm: Add allocation tag storage for system mode
b4a8eba target/arm: Create tagged ram when MTE is enabled
2ccff60 target/arm: Cache the Tagged bit for a page in MemTxAttrs
3154906 target/arm: Always pass cacheattr to get_phys_addr
9767e94 target/arm: Set PSTATE.TCO on exception entry
38e0afb target/arm: Implement data cache set allocation tags
6539e61 target/arm: Complete TBI clearing for user-only for SVE
9cb3267 target/arm: Add mte helpers for sve scatter/gather memory ops
68c5348 target/arm: Handle TBI for sve scalar + int memory ops
cdbe6a4 target/arm: Add mte helpers for sve scalar + int ff/nf loads
a38fad7 target/arm: Add mte helpers for sve scalar + int stores
0afc0c0 target/arm: Add mte helpers for sve scalar + int loads
a54faf2 target/arm: Add arm_tlb_bti_gp
ddc3017 target/arm: Tidy trans_LD1R_zpri
6fe827e target/arm: Use mte_check1 for sve LD1R
20dcf79 target/arm: Use mte_checkN for sve unpredicated stores
05d0e79 target/arm: Use mte_checkN for sve unpredicated loads
c0ebb0f target/arm: Add helper_mte_check_zva
664685f target/arm: Implement helper_mte_checkN
a7d6539 target/arm: Implement helper_mte_check1
f8b9d7f target/arm: Add gen_mte_checkN
9c2dcf8 target/arm: Add gen_mte_check1
447016c target/arm: Move regime_tcr to internals.h
12956a4 target/arm: Move regime_el to internals.h
c886a2f target/arm: Implement the access tag cache flushes
89f063e target/arm: Implement the LDGM, STGM, STZGM instructions
b2d4fba target/arm: Simplify DC_ZVA
73c7897 target/arm: Restrict the values of DCZID.BS under TCG
79e377e target/arm: Implement the STGP instruction
665a07a target/arm: Implement LDG, STG, ST2G instructions
144ee8d target/arm: Define arm_cpu_do_unaligned_access for user-only
6396699 target/arm: Implement the SUBP instruction
0ee3f9e target/arm: Implement the GMI instruction
6b20749 target/arm: Implement the ADDG, SUBG instructions
c83fbd1 target/arm: Revise decoding for disas_add_sub_imm
1a0adea target/arm: Implement the IRG instruction
dceed31 target/arm: Add MTE bits to tb_flags
e55acda target/arm: Add MTE system registers
d6e7faa target/arm: Add DISAS_UPDATE_NOCHAIN
5a5c51e target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
32aa9ac target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
06cb0fb target/arm: Add support for MTE to SCTLR_ELx
b7cbaa3 target/arm: Improve masking of SCR RES0 bits
a5a2984 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/46 Checking commit a5a2984f9455 (target/arm: Add isar tests for mte)
2/46 Checking commit b7cbaa3a682e (target/arm: Improve masking of SCR RES0 bits)
3/46 Checking commit 06cb0fb346a8 (target/arm: Add support for MTE to SCTLR_ELx)
4/46 Checking commit 32aa9acf6271 (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3)
5/46 Checking commit 5a5c51e63099 (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT)
6/46 Checking commit d6e7faab1b43 (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/46 Checking commit e55acdacb7c9 (target/arm: Add MTE system registers)
8/46 Checking commit dceed31be681 (target/arm: Add MTE bits to tb_flags)
9/46 Checking commit 1a0adea085f2 (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/46 Checking commit c83fbd1393b9 (target/arm: Revise decoding for disas_add_sub_imm)
11/46 Checking commit 6b207499c349 (target/arm: Implement the ADDG, SUBG instructions)
12/46 Checking commit 0ee3f9e74933 (target/arm: Implement the GMI instruction)
13/46 Checking commit 639669971961 (target/arm: Implement the SUBP instruction)
14/46 Checking commit 144ee8d3ccfa (target/arm: Define arm_cpu_do_unaligned_access for user-only)
15/46 Checking commit 665a07ad2896 (target/arm: Implement LDG, STG, ST2G instructions)
16/46 Checking commit 79e377e20409 (target/arm: Implement the STGP instruction)
17/46 Checking commit 73c7897861d4 (target/arm: Restrict the values of DCZID.BS under TCG)
18/46 Checking commit b2d4fba2a927 (target/arm: Simplify DC_ZVA)
19/46 Checking commit 89f063e1e72e (target/arm: Implement the LDGM, STGM, STZGM instructions)
20/46 Checking commit c886a2f2ae59 (target/arm: Implement the access tag cache flushes)
21/46 Checking commit 12956a4f828d (target/arm: Move regime_el to internals.h)
22/46 Checking commit 447016cebd06 (target/arm: Move regime_tcr to internals.h)
23/46 Checking commit 9c2dcf860acd (target/arm: Add gen_mte_check1)
24/46 Checking commit f8b9d7f9cea2 (target/arm: Add gen_mte_checkN)
25/46 Checking commit a7d65393dc26 (target/arm: Implement helper_mte_check1)
26/46 Checking commit 664685fb8d82 (target/arm: Implement helper_mte_checkN)
27/46 Checking commit c0ebb0fde795 (target/arm: Add helper_mte_check_zva)
28/46 Checking commit 05d0e794c710 (target/arm: Use mte_checkN for sve unpredicated loads)
29/46 Checking commit 20dcf793ab36 (target/arm: Use mte_checkN for sve unpredicated stores)
30/46 Checking commit 6fe827ec2022 (target/arm: Use mte_check1 for sve LD1R)
31/46 Checking commit ddc301735076 (target/arm: Tidy trans_LD1R_zpri)
32/46 Checking commit a54faf2d1d6b (target/arm: Add arm_tlb_bti_gp)
33/46 Checking commit 0afc0c0f79ec (target/arm: Add mte helpers for sve scalar + int loads)
34/46 Checking commit a38fad7262d9 (target/arm: Add mte helpers for sve scalar + int stores)
35/46 Checking commit cdbe6a4813d5 (target/arm: Add mte helpers for sve scalar + int ff/nf loads)
36/46 Checking commit 68c5348ab6db (target/arm: Handle TBI for sve scalar + int memory ops)
37/46 Checking commit 9cb3267a22fe (target/arm: Add mte helpers for sve scatter/gather memory ops)
38/46 Checking commit 6539e614c022 (target/arm: Complete TBI clearing for user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#57: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 38/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/46 Checking commit 38e0afbd1936 (target/arm: Implement data cache set allocation tags)
40/46 Checking commit 9767e94f1b3c (target/arm: Set PSTATE.TCO on exception entry)
41/46 Checking commit 3154906b1681 (target/arm: Always pass cacheattr to get_phys_addr)
42/46 Checking commit 2ccff60ed0a9 (target/arm: Cache the Tagged bit for a page in MemTxAttrs)
43/46 Checking commit b4a8ebafa261 (target/arm: Create tagged ram when MTE is enabled)
44/46 Checking commit fd1e477dc716 (target/arm: Add allocation tag storage for system mode)
45/46 Checking commit 68e0e2c8654f (target/arm: Enable MTE)
46/46 Checking commit 19fd1487595d (target/arm: Add arm,armv8.5-memtag to dtb)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
no-reply@patchew.org June 26, 2020, 5:07 a.m. | #3
Patchew URL: https://patchew.org/QEMU/20200626033144.790098-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200626033144.790098-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200626033144.790098-1-richard.henderson@linaro.org -> patchew/20200626033144.790098-1-richard.henderson@linaro.org
Switched to a new branch 'test'
f9c5338 target/arm: Add arm,armv8.5-memtag to dtb
50373ce target/arm: Enable MTE
5e43981 target/arm: Add allocation tag storage for system mode
b716019 target/arm: Create tagged ram when MTE is enabled
54dffdd target/arm: Cache the Tagged bit for a page in MemTxAttrs
e9d7c0c target/arm: Always pass cacheattr to get_phys_addr
5b4bb08 target/arm: Set PSTATE.TCO on exception entry
2374105 target/arm: Implement data cache set allocation tags
d00eb58 target/arm: Complete TBI clearing for user-only for SVE
a259ae4 target/arm: Add mte helpers for sve scatter/gather memory ops
a42b648 target/arm: Handle TBI for sve scalar + int memory ops
4b412c5 target/arm: Add mte helpers for sve scalar + int ff/nf loads
e0186f9 target/arm: Add mte helpers for sve scalar + int stores
c576e49 target/arm: Add mte helpers for sve scalar + int loads
ed24264 target/arm: Add arm_tlb_bti_gp
ff4e523 target/arm: Tidy trans_LD1R_zpri
44daf9e target/arm: Use mte_check1 for sve LD1R
4c9e8db target/arm: Use mte_checkN for sve unpredicated stores
d44ff24 target/arm: Use mte_checkN for sve unpredicated loads
f998d46 target/arm: Add helper_mte_check_zva
717954f target/arm: Implement helper_mte_checkN
65173b3 target/arm: Implement helper_mte_check1
c3c6b6e target/arm: Add gen_mte_checkN
4c7848f target/arm: Add gen_mte_check1
f2a85d3 target/arm: Move regime_tcr to internals.h
28cc6ee target/arm: Move regime_el to internals.h
2f468a1 target/arm: Implement the access tag cache flushes
fbdcf28 target/arm: Implement the LDGM, STGM, STZGM instructions
af47c61 target/arm: Simplify DC_ZVA
2462cc0 target/arm: Restrict the values of DCZID.BS under TCG
10f3a95 target/arm: Implement the STGP instruction
cf161ed target/arm: Implement LDG, STG, ST2G instructions
a871478 target/arm: Define arm_cpu_do_unaligned_access for user-only
e5e68d2 target/arm: Implement the SUBP instruction
59e4015 target/arm: Implement the GMI instruction
41e37a6 target/arm: Implement the ADDG, SUBG instructions
e16dacf target/arm: Revise decoding for disas_add_sub_imm
30e907e target/arm: Implement the IRG instruction
88bf5ec target/arm: Add MTE bits to tb_flags
42a90e2 target/arm: Add MTE system registers
4eebaf9 target/arm: Add DISAS_UPDATE_NOCHAIN
3803a5a target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
6dcc087 target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
1ffbabf target/arm: Add support for MTE to SCTLR_ELx
f5db6d8 target/arm: Improve masking of SCR RES0 bits
0529812 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/46 Checking commit 0529812ba00c (target/arm: Add isar tests for mte)
2/46 Checking commit f5db6d8b0561 (target/arm: Improve masking of SCR RES0 bits)
3/46 Checking commit 1ffbabf944e2 (target/arm: Add support for MTE to SCTLR_ELx)
4/46 Checking commit 6dcc0876172b (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3)
5/46 Checking commit 3803a5a8f556 (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT)
6/46 Checking commit 4eebaf929f15 (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/46 Checking commit 42a90e2dc7a7 (target/arm: Add MTE system registers)
8/46 Checking commit 88bf5ec2264c (target/arm: Add MTE bits to tb_flags)
9/46 Checking commit 30e907e6cbd7 (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/46 Checking commit e16dacf7de7d (target/arm: Revise decoding for disas_add_sub_imm)
11/46 Checking commit 41e37a609ce0 (target/arm: Implement the ADDG, SUBG instructions)
12/46 Checking commit 59e4015f372a (target/arm: Implement the GMI instruction)
13/46 Checking commit e5e68d267788 (target/arm: Implement the SUBP instruction)
14/46 Checking commit a87147851d90 (target/arm: Define arm_cpu_do_unaligned_access for user-only)
15/46 Checking commit cf161ed3a7e1 (target/arm: Implement LDG, STG, ST2G instructions)
16/46 Checking commit 10f3a9533353 (target/arm: Implement the STGP instruction)
17/46 Checking commit 2462cc02a351 (target/arm: Restrict the values of DCZID.BS under TCG)
18/46 Checking commit af47c6154ba2 (target/arm: Simplify DC_ZVA)
19/46 Checking commit fbdcf28bd7c3 (target/arm: Implement the LDGM, STGM, STZGM instructions)
20/46 Checking commit 2f468a147ad2 (target/arm: Implement the access tag cache flushes)
21/46 Checking commit 28cc6ee1e400 (target/arm: Move regime_el to internals.h)
22/46 Checking commit f2a85d318b32 (target/arm: Move regime_tcr to internals.h)
23/46 Checking commit 4c7848f867be (target/arm: Add gen_mte_check1)
24/46 Checking commit c3c6b6e91fe8 (target/arm: Add gen_mte_checkN)
25/46 Checking commit 65173b3f2b54 (target/arm: Implement helper_mte_check1)
26/46 Checking commit 717954fa82cc (target/arm: Implement helper_mte_checkN)
27/46 Checking commit f998d46b2bc4 (target/arm: Add helper_mte_check_zva)
28/46 Checking commit d44ff244144d (target/arm: Use mte_checkN for sve unpredicated loads)
29/46 Checking commit 4c9e8dbb0f8d (target/arm: Use mte_checkN for sve unpredicated stores)
30/46 Checking commit 44daf9e92a49 (target/arm: Use mte_check1 for sve LD1R)
31/46 Checking commit ff4e5239a817 (target/arm: Tidy trans_LD1R_zpri)
32/46 Checking commit ed242645700b (target/arm: Add arm_tlb_bti_gp)
33/46 Checking commit c576e49abee0 (target/arm: Add mte helpers for sve scalar + int loads)
34/46 Checking commit e0186f9efd46 (target/arm: Add mte helpers for sve scalar + int stores)
35/46 Checking commit 4b412c552991 (target/arm: Add mte helpers for sve scalar + int ff/nf loads)
36/46 Checking commit a42b648c561e (target/arm: Handle TBI for sve scalar + int memory ops)
37/46 Checking commit a259ae491cee (target/arm: Add mte helpers for sve scatter/gather memory ops)
38/46 Checking commit d00eb58f4686 (target/arm: Complete TBI clearing for user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#57: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 38/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/46 Checking commit 2374105a46e8 (target/arm: Implement data cache set allocation tags)
40/46 Checking commit 5b4bb0856135 (target/arm: Set PSTATE.TCO on exception entry)
41/46 Checking commit e9d7c0ce20a8 (target/arm: Always pass cacheattr to get_phys_addr)
42/46 Checking commit 54dffddc5b17 (target/arm: Cache the Tagged bit for a page in MemTxAttrs)
43/46 Checking commit b716019a48f9 (target/arm: Create tagged ram when MTE is enabled)
44/46 Checking commit 5e43981e3d60 (target/arm: Add allocation tag storage for system mode)
45/46 Checking commit 50373ce98b3a (target/arm: Enable MTE)
46/46 Checking commit f9c53383ab18 (target/arm: Add arm,armv8.5-memtag to dtb)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
no-reply@patchew.org June 26, 2020, 5:25 a.m. | #4
Patchew URL: https://patchew.org/QEMU/20200626033144.790098-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200626033144.790098-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200626033144.790098-1-richard.henderson@linaro.org -> patchew/20200626033144.790098-1-richard.henderson@linaro.org
Switched to a new branch 'test'
ea14124 target/arm: Add arm,armv8.5-memtag to dtb
026e589 target/arm: Enable MTE
fa6356a target/arm: Add allocation tag storage for system mode
f2fc923 target/arm: Create tagged ram when MTE is enabled
712e523 target/arm: Cache the Tagged bit for a page in MemTxAttrs
1c7fdd5 target/arm: Always pass cacheattr to get_phys_addr
945b78b target/arm: Set PSTATE.TCO on exception entry
c922cc0 target/arm: Implement data cache set allocation tags
bad8858 target/arm: Complete TBI clearing for user-only for SVE
eb44aa0 target/arm: Add mte helpers for sve scatter/gather memory ops
fd47bb8 target/arm: Handle TBI for sve scalar + int memory ops
d101c09 target/arm: Add mte helpers for sve scalar + int ff/nf loads
7b66cd4 target/arm: Add mte helpers for sve scalar + int stores
460243b target/arm: Add mte helpers for sve scalar + int loads
0b0dbb6 target/arm: Add arm_tlb_bti_gp
942f9c5 target/arm: Tidy trans_LD1R_zpri
a2965d5 target/arm: Use mte_check1 for sve LD1R
70061de target/arm: Use mte_checkN for sve unpredicated stores
4d333a6 target/arm: Use mte_checkN for sve unpredicated loads
43f282a target/arm: Add helper_mte_check_zva
c6f0339 target/arm: Implement helper_mte_checkN
4bd0d5f target/arm: Implement helper_mte_check1
edcfda1 target/arm: Add gen_mte_checkN
c7a4e6b target/arm: Add gen_mte_check1
f739caf target/arm: Move regime_tcr to internals.h
dd91a4a target/arm: Move regime_el to internals.h
4b498b4 target/arm: Implement the access tag cache flushes
045e5a9 target/arm: Implement the LDGM, STGM, STZGM instructions
9ee3f3a target/arm: Simplify DC_ZVA
e4b03e8 target/arm: Restrict the values of DCZID.BS under TCG
47691b4 target/arm: Implement the STGP instruction
72b11e0 target/arm: Implement LDG, STG, ST2G instructions
042564c target/arm: Define arm_cpu_do_unaligned_access for user-only
9b9d7e8 target/arm: Implement the SUBP instruction
9563b5f target/arm: Implement the GMI instruction
bff6771 target/arm: Implement the ADDG, SUBG instructions
d0e93a7 target/arm: Revise decoding for disas_add_sub_imm
515496c target/arm: Implement the IRG instruction
e7782e6 target/arm: Add MTE bits to tb_flags
11bfa4a target/arm: Add MTE system registers
6052630 target/arm: Add DISAS_UPDATE_NOCHAIN
1932e01 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
c9ebd4b target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
e3eae8a target/arm: Add support for MTE to SCTLR_ELx
cd16db3 target/arm: Improve masking of SCR RES0 bits
2c4afe3 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/46 Checking commit 2c4afe349858 (target/arm: Add isar tests for mte)
2/46 Checking commit cd16db3d6f0c (target/arm: Improve masking of SCR RES0 bits)
3/46 Checking commit e3eae8ac6f72 (target/arm: Add support for MTE to SCTLR_ELx)
4/46 Checking commit c9ebd4b7538b (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3)
5/46 Checking commit 1932e0177665 (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT)
6/46 Checking commit 60526300071c (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/46 Checking commit 11bfa4af1833 (target/arm: Add MTE system registers)
8/46 Checking commit e7782e6fcc94 (target/arm: Add MTE bits to tb_flags)
9/46 Checking commit 515496c0a8bf (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/46 Checking commit d0e93a779105 (target/arm: Revise decoding for disas_add_sub_imm)
11/46 Checking commit bff67715f6b3 (target/arm: Implement the ADDG, SUBG instructions)
12/46 Checking commit 9563b5f54347 (target/arm: Implement the GMI instruction)
13/46 Checking commit 9b9d7e8534b3 (target/arm: Implement the SUBP instruction)
14/46 Checking commit 042564cfe6c3 (target/arm: Define arm_cpu_do_unaligned_access for user-only)
15/46 Checking commit 72b11e0ba319 (target/arm: Implement LDG, STG, ST2G instructions)
16/46 Checking commit 47691b45881c (target/arm: Implement the STGP instruction)
17/46 Checking commit e4b03e8f5284 (target/arm: Restrict the values of DCZID.BS under TCG)
18/46 Checking commit 9ee3f3a3393c (target/arm: Simplify DC_ZVA)
19/46 Checking commit 045e5a90e6bc (target/arm: Implement the LDGM, STGM, STZGM instructions)
20/46 Checking commit 4b498b4743c1 (target/arm: Implement the access tag cache flushes)
21/46 Checking commit dd91a4ac8cb5 (target/arm: Move regime_el to internals.h)
22/46 Checking commit f739caf553f2 (target/arm: Move regime_tcr to internals.h)
23/46 Checking commit c7a4e6bccd6a (target/arm: Add gen_mte_check1)
24/46 Checking commit edcfda13df2d (target/arm: Add gen_mte_checkN)
25/46 Checking commit 4bd0d5fb2060 (target/arm: Implement helper_mte_check1)
26/46 Checking commit c6f033940b2e (target/arm: Implement helper_mte_checkN)
27/46 Checking commit 43f282a31501 (target/arm: Add helper_mte_check_zva)
28/46 Checking commit 4d333a670294 (target/arm: Use mte_checkN for sve unpredicated loads)
29/46 Checking commit 70061dee2c97 (target/arm: Use mte_checkN for sve unpredicated stores)
30/46 Checking commit a2965d554b55 (target/arm: Use mte_check1 for sve LD1R)
31/46 Checking commit 942f9c5c274f (target/arm: Tidy trans_LD1R_zpri)
32/46 Checking commit 0b0dbb6dabac (target/arm: Add arm_tlb_bti_gp)
33/46 Checking commit 460243b91717 (target/arm: Add mte helpers for sve scalar + int loads)
34/46 Checking commit 7b66cd4ba344 (target/arm: Add mte helpers for sve scalar + int stores)
35/46 Checking commit d101c0961f2e (target/arm: Add mte helpers for sve scalar + int ff/nf loads)
36/46 Checking commit fd47bb8822d5 (target/arm: Handle TBI for sve scalar + int memory ops)
37/46 Checking commit eb44aa08aa52 (target/arm: Add mte helpers for sve scatter/gather memory ops)
38/46 Checking commit bad88583af69 (target/arm: Complete TBI clearing for user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#57: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 38/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/46 Checking commit c922cc099458 (target/arm: Implement data cache set allocation tags)
40/46 Checking commit 945b78b9b5ce (target/arm: Set PSTATE.TCO on exception entry)
41/46 Checking commit 1c7fdd591266 (target/arm: Always pass cacheattr to get_phys_addr)
42/46 Checking commit 712e523bf512 (target/arm: Cache the Tagged bit for a page in MemTxAttrs)
43/46 Checking commit f2fc923a1075 (target/arm: Create tagged ram when MTE is enabled)
44/46 Checking commit fa6356aadd32 (target/arm: Add allocation tag storage for system mode)
45/46 Checking commit 026e5898ca2d (target/arm: Enable MTE)
46/46 Checking commit ea141247b110 (target/arm: Add arm,armv8.5-memtag to dtb)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
Peter Maydell June 26, 2020, 3:14 p.m. | #5
On Fri, 26 Jun 2020 at 04:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Version 9 incorporates some review:

>

>   * Adjust some commentary.

>   * Added an assert for tbi in aarch64_tr_init_disas_context

>   * Split arm,armv8.5-memtag to a new, final, patch.  We might

>     just leave this one out of qemu mainline until the kernel

>     patch set that requires it gets merged.

>


Thanks, applied all but patch 46 to target-arm.next.

-- PMM