| Message ID | 20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com |
|---|---|
| Headers | show |
| Series | iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) | expand |
On 13/05/17 10:47, shameer wrote: > This replaces the existing broken_prefetch_cmd quirk using > the new erratum framework. > > Signed-off-by: shameer <shameerali.kolothum.thodi@huawei.com> > --- > arch/arm64/Kconfig | 10 +++++++++- > drivers/iommu/arm-smmu-v3.c | 36 ++++++++++-------------------------- > 2 files changed, 19 insertions(+), 27 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index a39029b..21d61ff 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -508,8 +508,16 @@ config QCOM_FALKOR_ERRATUM_1009 > > If unsure, say Y. > > -endmenu > +config HISILICON_ERRATUM_161010701 > + bool "HiSilicon erratum 161010701: Skip SMMU Prefetch Cmd" > + default y > + help > + On HiSilicon Hip06/Hip07 platforms, the SMMU v3 doesn't support the > + CMD_PREFETCH_CFG. This will skip the prefetch cmd usage. > > + If unsure, say Y. We don't need a config. This feature (not to mention others like it) is runtime-detected, and has effectively zero execution overhead and negligible Image-size overhead either way; why would anyone ever turn it off? Robin. > + > +endmenu > > choice > prompt "Page size" > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index f20d5d5..14538cb 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -650,16 +650,6 @@ struct arm_smmu_domain { > struct iommu_domain domain; > }; > > -struct arm_smmu_option_prop { > - u32 opt; > - const char *prop; > -}; > - > -static struct arm_smmu_option_prop arm_smmu_options[] = { > - { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, > - { 0, NULL}, > -}; > - > enum smmu_erratum_match_type { > se_match_dt, > }; > @@ -677,7 +667,17 @@ struct smmu_erratum_workaround { > }; > > static const struct smmu_erratum_workaround smmu_workarounds[] = { > +#ifdef CONFIG_HISILICON_ERRATUM_161010701 > + { > + .match_type = se_match_dt, > + .id = "hisilicon,erratum-161010701", > + .desc_str = "HiSilicon erratum 161010701", > + .enable = erratum_skip_prefetch_cmd, > + }, > +#endif > + { > > + }, > }; > > typedef bool (*se_match_fn_t)(const struct smmu_erratum_workaround *, > @@ -735,20 +735,6 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) > return container_of(dom, struct arm_smmu_domain, domain); > } > > -static void parse_driver_options(struct arm_smmu_device *smmu) > -{ > - int i = 0; > - > - do { > - if (of_property_read_bool(smmu->dev->of_node, > - arm_smmu_options[i].prop)) { > - smmu->options |= arm_smmu_options[i].opt; > - dev_notice(smmu->dev, "option %s\n", > - arm_smmu_options[i].prop); > - } > - } while (arm_smmu_options[++i].opt); > -} > - > /* Low-level queue manipulation functions */ > static bool queue_full(struct arm_smmu_queue *q) > { > @@ -2695,8 +2681,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, > else > ret = 0; > > - parse_driver_options(smmu); > - > smmu_check_workarounds(smmu, se_match_dt, dev->of_node); > > if (of_dma_is_coherent(dev->of_node)) > -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova alloactions. To implement this quirk, the following changes are incorporated into smmu-v3: 1. Added a general erratum framework based on arm_arch_timer erratum framework. The intention is to have a common framework for dt and acpi based quirk implementations. 2. Replaced the existing hisilicon, broken_prefetch_cmd quirk using the new erratum framework (erratum-161010701) 3. Introduced a ACPI based quirk for erratum-161010801. 4. ACPI CSRT vendor specific blobs are used to pass the reserve address region info on these platforms. Also please note that this patchset is based on Robin's patch series "acpica: iort: Update SMMU models for IORT rev. C". https://lkml.org/lkml/2017/5/12/211 Thanks, Shameer shameer (7): iommu/arm-smmu-v3: Add erratum framework structures iommu/arm-smmu-v3: Add erratum framework functions iommu/arm-smmu-v3: Replace the device tree binding for hisilicon broken prefetch cmd with erratum id iommu/arm-smmu-v3: Enable HiSilicon erratum 161010701 iommu/arm-smmu-v3: Enable ACPI based HiSilicon erratum 161010701 iommu/arm-smmu-v3: Rearrange msi resv alloc functions iommu/arm-smmu-v3: Enable ACPI based HiSilicon erratum 161010801 .../devicetree/bindings/iommu/arm,smmu-v3.txt | 2 +- arch/arm64/Kconfig | 20 +- drivers/iommu/arm-smmu-v3.c | 225 ++++++++++++++++++--- 3 files changed, 218 insertions(+), 29 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html