From patchwork Thu May 18 10:35:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100080 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp650560qge; Thu, 18 May 2017 03:36:38 -0700 (PDT) X-Received: by 10.98.24.200 with SMTP id 191mr3689416pfy.207.1495103798410; Thu, 18 May 2017 03:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495103798; cv=none; d=google.com; s=arc-20160816; b=EbgBPSdcOFykBz7nt/nTEPhl08iCyWs5PlBNy96lF3J3q4C/XMt7joA1qlaY3GJHiK 3oDnT9wd9MRxhmGTvd8y1wYa7vBULzYjZ8ZW14HvLI35tRBNL7D9aejykIvwvNXJOCip JQfDs+OhgUmf+NZctaaZ+EX06UM0wyrX/IkcIsO3ORRcTdNq8IU3qkc6zrRXF7DLuaKS 9wxGEWrTEj/DKNrFVBNFHC2JLDbwAbCqR22ig11HC/loEaept63Ncp+EH2o7hh3cZHGv R9wK5Qdq8pScT40iE84Ad5gth7CWrfHQRqaptJukXRwxkvEzhPToiriTxxVl55Q1SXUa 5bKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=D+Md/62chYUk4gGAswEPWHiTPkZPWYcEPtCR5KCbzBE=; b=e1ZIyzXjhG1tyhxKDAFZUysQbLjLYP8WtcE9XxRvQoC4YhLUt0dQnZA/5ms8BnUVJD l1QO8XPvXBk+73mfJEb/gQtpFZcMBAi6Pmbam+WrB5Igbinz07AjkwUJYuoKFRWgEZXg XmL2gcZyH0u6yDoSx5UwTuWl5AYsqcHm55i1eOu9mNk4bMCtn4MVZEK7kj66rPhks4/A +Lu2zvHxNZ5YCkwoQZGu1U9T0yFCPB3Sr5HPjnxw0uUsl43AMQiNBmuwW5s5V0otmR7K 6rnPKI6mW06oitpYeTN+oeImZo50BKshjCvwT3kmmIWNRjUy65HNK2BcIYV9QUfj3GS3 IipQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l191si4779159pge.251.2017.05.18.03.36.38; Thu, 18 May 2017 03:36:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755574AbdERKgZ (ORCPT + 25 others); Thu, 18 May 2017 06:36:25 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6786 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754157AbdERKgW (ORCPT ); Thu, 18 May 2017 06:36:22 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOU84643; Thu, 18 May 2017 18:36:16 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Thu, 18 May 2017 18:36:07 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v3 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Thu, 18 May 2017 11:35:48 +0100 Message-ID: <1495103748-7876-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495103748-7876-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495103748-7876-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.591D7921.000B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 124ee0d20cd549db685deec4b9982716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni Reviewed-by: Christoph Hellwig --- drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 4d16cf2..6a32b42 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -123,6 +123,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the