From patchwork Fri May 19 04:25:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 100146 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp140994qge; Thu, 18 May 2017 21:26:46 -0700 (PDT) X-Received: by 10.99.124.94 with SMTP id l30mr8072094pgn.55.1495168006335; Thu, 18 May 2017 21:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495168006; cv=none; d=google.com; s=arc-20160816; b=Fr2iSpyVvG+mTgj2N0a8/TcC3Awosbr4CLQXOED6poE6lsrCW8Or97tlmwLviWgH6v bgG4o5eN1P2GBX8vIPGr/H2tDLow+DFApAHqyiURvT5HvuLY50GwiAZEpzxduBCoFaCq lXTvL9fVhMtRTD7KdBjkfRahfTR2heUd81A8s615aJg1VdHW18BK+1ZOdB8N70EUJm+k i5z9V3XsXvwo28C+EX7LUX8HnqjVM9mAFvAXThrH5UTK745pbQcWaKQsk25Q6u7H0gFh RwELsLN/xXaXpgMBYDWCp9HnDpcSKoaKuSHPgsftapi2mblX4CuT+tPWjfZ1D9rUOCTV sT5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=C2MVggQI5FIxB7AFkJBKKdd6ewELSNqFg/FqKXCWlDc=; b=brVqYHb93UUDYZqr2dNNed9wHl27sT+YFHmxGO5NzlScJq1kMT1O5tmhIs58DYdnwM ik1soMmOyLOE6krxkVVi7sqNoY6MfjlAczp1gzYKShbTnEcn/EQFLA79QMBsrO/dJsaF yuQ1aV9urCGfqChjAuwTxD0vvrDBK25bG89gjJncizxyBobdoX77wE+K2kH/usOjEjG6 cFwsI3Ab0GO1dxcUAYc0MC3A/dggXWkMZCOo6DPQLTRJeMR1L056vRJ9mdppKXYUqZuW US1WfdQ+tQETbXVMFLu9rBwtoCEoUia36TkjNDWP73VSLFD4vqyUCMkqE7TcWkwoQpFs dPxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z185si7237807pgb.292.2017.05.18.21.26.46; Thu, 18 May 2017 21:26:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752437AbdESE0i (ORCPT + 10 others); Fri, 19 May 2017 00:26:38 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:35588 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752265AbdESE0f (ORCPT ); Fri, 19 May 2017 00:26:35 -0400 Received: by mail-pg0-f51.google.com with SMTP id q125so32317377pgq.2 for ; Thu, 18 May 2017 21:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TCzWnzJHkW2SFRPz4eiJs5qhJ0x1GgU4cRW9E8ItAJo=; b=H7A6a7dlhfsD5JlvHxRs9Bryj7q+1Ifhi+pq++udFvSUeHJ0WYH1B+zhbAfQDLLU/R ec+HhUdXRlFNsK9W8E0rJBhdBhwBult911ShFiK9/Pj1VgYkULlFslOMbTJ4M3X+UqL9 KpCgsXdSCepb96KwZ+fgUmRypJEm9Ndkmz8zg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TCzWnzJHkW2SFRPz4eiJs5qhJ0x1GgU4cRW9E8ItAJo=; b=JeV78olFPFTtisKw+AikeemWXXTSeKVm3YG4W/pvC8/iY0eqx0NdK0tpHwj9Jag94p vJonscYRejtTR82uCIGs+nYqOXwDRBs+wCIuF5AVKMtSzE8rliFkCnMbmKjNEYjx/px4 tr+CyX0H5gDyfOLW8UlcsNiAjUIarEMFc63y3Bc5v0y3TnGzS0NdNTmP78yaFA7CWb1x rGFD6ywE/0Lpueg8AhtiVmEU5Ez4L0Z7HQngTzTXsFsHMPfSIFDpCb13KeHIG1AjJGhS ynne9XVKil5D0lQcSl9WF9zZT3xYCMsEd0PrwSNsRLuPNgvy7vRhJNv2I77gMoH55/Pp tAEw== X-Gm-Message-State: AODbwcAWh9gv+8d6SdY1SpW8S3uPCwo+VGFLZgv3GvM9XOJhw+a+00+M hRIZixXpCp+KhXSe X-Received: by 10.84.202.163 with SMTP id x32mr8986719pld.51.1495167989193; Thu, 18 May 2017 21:26:29 -0700 (PDT) Received: from localhost.localdomain (li637-108.members.linode.com. [106.186.117.108]) by smtp.gmail.com with ESMTPSA id c29sm5823259pfj.101.2017.05.18.21.26.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 May 2017 21:26:27 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Wei Xu , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v10 01/10] coresight: bindings for CPU debug module Date: Fri, 19 May 2017 12:25:48 +0800 Message-Id: <1495167957-14923-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> References: <1495167957-14923-1-git-send-email-leo.yan@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..2982912 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,49 @@ +* CoreSight CPU Debug Component: + +CoreSight CPU debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be "arm,coresight-cpu-debug"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the CPU phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to the debug power domain. We use "power-domains" + binding to turn on the debug logic if it has own dedicated + power domain and if necessary to use "cpuidle.off=1" or + "nohlt" in the kernel command line or sysfs node to + constrain idle states to ensure registers in the CPU power + domain are accessible. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };