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[209.132.180.67]) by mx.google.com with ESMTP id f8si30219256pln.39.2017.05.26.00.39.07; Fri, 26 May 2017 00:39:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761790AbdEZHjF (ORCPT + 7 others); Fri, 26 May 2017 03:39:05 -0400 Received: from mail-pf0-f169.google.com ([209.85.192.169]:35207 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1163750AbdEZHjD (ORCPT ); Fri, 26 May 2017 03:39:03 -0400 Received: by mail-pf0-f169.google.com with SMTP id n23so4133703pfb.2 for ; Fri, 26 May 2017 00:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oKZuGARDabkKk0KFrbaiazCbfww3IQtHeveQuqvAKUw=; b=kIUWRSk9YDLaAEvCp+zKyBCNYXat4Wl2qRLxu5++ctBMMNIU5PSu6xYcIre07ltF+h A9xuhJRiWrmzschABU/K5F0+p38z1MWYQyI7jMsIE8r6ieytCD6e+bi0WUkgfsJSXMYS 4z7P7rJbmrWXTRvUqSNh/VeP6DWYAgKffeLjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oKZuGARDabkKk0KFrbaiazCbfww3IQtHeveQuqvAKUw=; b=XrELNdAaLiv4ZTbGFHZvDA3ZVuDe7199Jq3IQFG2NJMs1zN6nVIZuSBH7frhy7RuUa 9J1/e4PxyC6TtMzixHrj3Bemgt/sKxFalBFlI8KfZkuz+ioT/EhzEDvY+0sPFewS68K6 X0bvvNk+P/H3wXWOlqMff4aTENU9wPy6QeQ7lNCXpdpEyBOvpRdfb5AWmVlfK/hNCifP nBDbY0tVTSrnr4+EMP9K66YrTvYzb2HzyiedrsYbWHnxs0yy0e9r/JsQCjRWoPuu3RUQ V46OgNO2YebzCTX9LipzGPwia5pxZ8tXcLP6zUE1/abXCxlMo1UJHi8gaqDcJFSuRK4i 97Ug== X-Gm-Message-State: AODbwcCkgrv0vU/pAVU8xiX2LQHYBB+aPb9o9LhWcaynwqPT1mOYGFlE Uc9QOwpuJWk6xD0B X-Received: by 10.84.218.134 with SMTP id r6mr3655224pli.190.1495784324069; Fri, 26 May 2017 00:38:44 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id t3sm19106334pfl.60.2017.05.26.00.38.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 May 2017 00:38:43 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zheng Shaobo Subject: [PATCH v2 3/3] clk: hi3660: Set PPLL2 to 2880M Date: Fri, 26 May 2017 15:38:21 +0800 Message-Id: <20170526073821.25971-4-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170526073821.25971-1-guodong.xu@linaro.org> References: <20170526073821.25971-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Zhong Kaihua Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua Signed-off-by: Zheng Shaobo --- drivers/clk/hisilicon/clk-hi3660.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Zhangfei Gao diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 67c4d44..eb9ba41 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -20,7 +20,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, }, { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, }, { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, }, - { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 960000000, }, + { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000, }, { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, }, { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, }, { HI3660_PCLK, "pclk", NULL, 0, 20000000, }, @@ -42,7 +42,7 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, }, { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, }, { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, }, - { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 2, 0, }, + { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, }, { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, }, { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },