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[54.225.227.206]) by mx.google.com with ESMTP id p19si18694219qtg.171.2017.06.01.02.45.45; Thu, 01 Jun 2017 02:45:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3E045609B3; Thu, 1 Jun 2017 09:45:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A295960A2E; Thu, 1 Jun 2017 09:44:44 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 41CF3609AA; Thu, 1 Jun 2017 09:44:36 +0000 (UTC) Received: from mail-wm0-f44.google.com (mail-wm0-f44.google.com [74.125.82.44]) by lists.linaro.org (Postfix) with ESMTPS id 5F1BC609DC for ; Thu, 1 Jun 2017 09:44:13 +0000 (UTC) Received: by mail-wm0-f44.google.com with SMTP id b84so151102789wmh.0 for ; Thu, 01 Jun 2017 02:44:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1mt0XXH2zyDsaF1YI3aKgzBHmMSpRkgrngQcST+wDvA=; b=lwuMYoAv08Sgyka3uqemhFvGKeYVyGV+7BOUwK/YkuridK8bvpomm/h4mJMqMcvi+E Jaqv45lDfbYH7IZX3JVQr8gSJcokKFdA5YcmCxVmSD27nP1v7Ign29SzyTRLOXZA7eMD zFdF2JENKIE98UR/DYVJ6gAjdWt+XJq0HWii1rgWsqzgYhSoTjqSqX+x9SfmjROAzwfn FTKKw7xO+WaCvbQjFPYxTJ/i096lTHK5Szc/gK74xf88ZsKYYpLbvxIWq0KXrhOdjolN pBUrOsCHC3IFEVwLdlO7vih2M8EyutHds7TXEZJLULE2ai/gSDCZq0YjrscN7MMganP9 w8Uw== X-Gm-Message-State: AODbwcCOtOsjVpGvpq9w+Bj14VTtVS56m9R7sIMyADmF1UgmCYfFbaaN 8Y96fjWUKqWxevQlKn1fd0ql X-Received: by 10.28.98.8 with SMTP id w8mr8696924wmb.121.1496310252297; Thu, 01 Jun 2017 02:44:12 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:11 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:53 +0000 Message-Id: <20170601094353.16235-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 6/6] Platforms/AMD/Styx: align UEFI PCI bus range with DT/ACPI descriptions X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The DT and ACPI descriptions of the PCIe root complex only specify a bus range of [0x0, 0x7f]. So let's use the same range in UEFI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index b4893ca34587..98f5c9452dcd 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -423,7 +423,7 @@ DEFINE DO_KCS = 1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 gArmTokenSpaceGuid.PcdPciBusMin|0x0 - gArmTokenSpaceGuid.PcdPciBusMax|0xFF + gArmTokenSpaceGuid.PcdPciBusMax|0x7F gArmTokenSpaceGuid.PcdPciIoBase|0x1000 gArmTokenSpaceGuid.PcdPciIoSize|0xF000