From patchwork Thu Jun 1 17:10:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100956 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859257obc; Thu, 1 Jun 2017 10:16:21 -0700 (PDT) X-Received: by 10.55.68.81 with SMTP id r78mr3173994qka.102.1496337381170; Thu, 01 Jun 2017 10:16:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337381; cv=none; d=google.com; s=arc-20160816; b=gbooPvipxsBvPfLd+9UciYPrlTcW8zdEfwp8v3fOPu09Iq7VJt+Jqs9COI5e0q1X/5 DiZkKO2NDNdvSoQIg4PlVUg3iXrpqpRfO+Tou2gX7MFAa1Mp4ju37++Ilwou0Q1sPGe5 Uo/RQQLEX0EMGB75pfnfTzNpOETq3h4P3mGJB9dAsmCmvBc8DJYP+0njbxRORH0+XOrd C6TV7oxrw5/D1om/G20HiQq9+MTh2XJ4lN5CVvQZL/RIphXfmpTRWbHdBl/4+qjmdWfG vU31A5njbojlkzWc83rgVsYqOi3bhwoC1fu8QxAyWTKV8y2QgNqAeaus22hftCbyGUBl U6AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=oHFs9RfriLotcTTyn7OGTLs1DKIjU6LW6+KC14thr5M=; b=uWkZnjUhB41bTRlwhx1gCegUNCOKF7hj2BhkPSma/f1jsY03B7MtZMlEJTeRMOGFE2 95BMLXKJwkpuh5W5/NzkgwyDhFmU6trjQIdQ+ze7Cymam159NIxau/d/CFa+O66Gzt85 7smpzXvwneAFZBgjVNCdt/RAri45IEzqpTzhPt16hGOHC2iEibwAS0yOVt0xuG6pdfQz zta1neIFNafFUccvxpHpgt5fLfWmfFLMfSLjFpH4ySaTsrFDH1VLYsjC/pEccPLvTc9h Ze+BypzxYS+hC10vba4o746G4/z4mi8d7us/QHO3TEEr2n6xo2XKeV2dtAnQ4NyDyCd8 i71Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r2si20547546qtc.37.2017.06.01.10.16.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:16:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGThq-0005uC-Fy for patch@linaro.org; Thu, 01 Jun 2017 13:16:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcV-00014Y-Ln for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcU-00068X-An for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcU-00067A-2G for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcQ-0007Pp-Qw for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:18 +0100 Message-Id: <1496337035-30213-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/27] arm: Clean up handling of no-MPU PMSA CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ARM CPUs come in two flavours: * proper MMU ("VMSA") * only an MPU ("PMSA") For PMSA, the MPU may be implemented, or not (in which case there is default "always acts the same" behaviour, but it isn't guest programmable). QEMU is a bit confused about how we indicate this: we have an ARM_FEATURE_MPU, but it's not clear whether this indicates "PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we use it for one purpose and sometimes the other. Currently trying to implement a PMSA-without-MPU core won't work correctly because we turn off the ARM_FEATURE_MPU bit and then a lot of things which should still exist get turned off too. As the first step in cleaning this up, rename the feature bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with or without MPU). Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 2 +- target/arm/cpu.c | 12 ++++++------ target/arm/helper.c | 12 ++++++------ target/arm/machine.c | 2 +- 4 files changed, 14 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cadec09..cb1d696 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1181,7 +1181,7 @@ enum arm_features { ARM_FEATURE_V6K, ARM_FEATURE_V7, ARM_FEATURE_THUMB2, - ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ + ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ ARM_FEATURE_VFP3, ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4e8fe1c..f844af5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -593,7 +593,7 @@ static void arm_cpu_post_init(Object *obj) &error_abort); } - if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -689,7 +689,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && - !arm_feature(env, ARM_FEATURE_MPU)) { + !arm_feature(env, ARM_FEATURE_PMSA)) { /* v7VMSA drops support for the old ARMv5 tiny pages, so we * can use 4K pages. */ @@ -764,10 +764,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (!cpu->has_mpu) { - unset_feature(env, ARM_FEATURE_MPU); + unset_feature(env, ARM_FEATURE_PMSA); } - if (arm_feature(env, ARM_FEATURE_MPU) && + if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7)) { uint32_t nr = cpu->pmsav7_dregion; @@ -867,7 +867,7 @@ static void arm946_initfn(Object *obj) cpu->dtb_compatible = "arm,arm946"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_MPU); + set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); cpu->midr = 0x41059461; cpu->ctr = 0x0f004006; @@ -1079,7 +1079,7 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_MPU); + set_feature(&cpu->env, ARM_FEATURE_PMSA); cpu->midr = 0x411fc153; /* r1p3 */ cpu->id_pfr0 = 0x0131; cpu->id_pfr1 = 0x001; diff --git a/target/arm/helper.c b/target/arm/helper.c index 791332c..404bfdb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -485,7 +485,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) + if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. @@ -4615,7 +4615,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v6k_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7MP) && - !arm_feature(env, ARM_FEATURE_MPU)) { + !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { @@ -4969,7 +4969,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } - if (arm_feature(env, ARM_FEATURE_MPU)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { if (arm_feature(env, ARM_FEATURE_V6)) { /* PMSAv6 not implemented */ assert(arm_feature(env, ARM_FEATURE_V7)); @@ -5131,7 +5131,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } define_arm_cp_regs(cpu, id_cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_MPU)) { + if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); @@ -8442,7 +8442,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* pmsav7 has special handling for when MPU is disabled so call it before * the common MMU/MPU disabled check below. */ - if (arm_feature(env, ARM_FEATURE_MPU) && + if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7)) { *page_size = TARGET_PAGE_SIZE; return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, @@ -8457,7 +8457,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return 0; } - if (arm_feature(env, ARM_FEATURE_MPU)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { /* Pre-v7 MPU */ *page_size = TARGET_PAGE_SIZE; return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, diff --git a/target/arm/machine.c b/target/arm/machine.c index d8094a8..ac6b758 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -142,7 +142,7 @@ static bool pmsav7_needed(void *opaque) ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; - return arm_feature(env, ARM_FEATURE_MPU) && + return arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7); }