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[209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.36; Wed, 07 Jun 2017 14:28:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751541AbdFGV2f (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:35 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:64590 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751469AbdFGV2e (ORCPT ); Wed, 7 Jun 2017 17:28:34 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRcDK007827; Wed, 7 Jun 2017 16:27:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870858; bh=/YisFtzfZ/XRMuKJwUSKz97zX3ABEZrh2bBGnTPBgGU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f6yQ8/KuMO3eAa5votZUkRhiPUT82cHQEKl+KXg0Lgcc2rrk7hVQkSGA3onZTsWji hd7I/OFfINpguhPduDcEmgYzCz9jd8PFKSWuyN1KW1MOk7JQvED8mZzDFrxB6P68a0 Ge1qW77FdC4o+VNP4U8qdnF9eAmh/50MwrPEnWRE= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRX5M010069; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWoP014167; Wed, 7 Jun 2017 16:27:32 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307110; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 3/6] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL Date: Wed, 7 Jun 2017 16:27:27 -0500 Message-ID: <20170607212730.33002-4-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IPU1 functional clock is actually the output of a mux clock, ipu1_gfclk_mux. The mux clock is sourced by default from the DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL is configured properly. Reconfigure the mux clock to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1 and IPU2 are running from the same clock and clocked at the same nominal frequency of 425 MHz. This also ensures that IPU1 functional clock is always configured properly and becomes independent of the state of the ABE DPLL on all boards. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3330738e4c6e..cfaf27215901 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -791,6 +791,8 @@ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; ti,bit-shift = <24>; reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {