[09/30,ARM] Move cpu and architecture option name parsing code to arm-common.c

Message ID bcfc2ba91b99cbfdd475d5f45d1e386ad6d99ad0.1497004220.git.Richard.Earnshaw@arm.com
State New
Headers show
Series
  • Reworking the -mcpu, -march and -mfpu options
Related show

Commit Message

Richard Earnshaw (lists) June 9, 2017, 12:53 p.m.
This patch has no functional change.  The code used for parsing -mcpu,
-mtune and -march options is simply moved from arm.c arm-common.c.
The list of FPU options is also moved.  Subsequent patches will make
use of this within the driver.

Some small adjustments are needed as a consequence of moving the
definitions of the data objects to another object file, in that we
no-longer have direct access to the size of the object.

	* common/config/arm/arm-common.c (arm_initialize_isa): Moved here from
	config/arm/arm.c.
	(arm_print_hint_for_cpu_option): Likewise.
	(arm_print_hint_for_arch_option): Likewise.
	(arm_parse_cpu_option_name): Likewise.
	(arm_parse_arch_option_name): Likewise.
	* config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number
	of entries in the all_fpus list.
	* config/arm/arm-protos.h (all_architectures, all_cores): Declare.
	(arm_parse_cpu_option_name): Declare.
	(arm_parse_arch_option_name): Declare.
	(arm_parse_option_features): Declare.
	(arm_intialize_isa): Declare.
	* config/arm/parsecpu.awk (gen_data): Move CPU and architecture
	data tables to ...
	(gen_comm_data): ... here.  Make definitions non-static.
	* config/arm/arm-cpu-data.h: Regenerated.
	* config/arm/arm-cpu-cdata.h: Regenerated.
---
 gcc/common/config/arm/arm-common.c |  190 +++
 gcc/config/arm/arm-cpu-cdata.h     | 2580 ++++++++++++++++++++++++++++++++++++
 gcc/config/arm/arm-cpu-data.h      | 2580 ------------------------------------
 gcc/config/arm/arm-protos.h        |   12 +
 gcc/config/arm/arm.c               |  190 +--
 gcc/config/arm/parsecpu.awk        |   69 +-
 6 files changed, 2819 insertions(+), 2802 deletions(-)

Comments

Richard Earnshaw (lists) June 13, 2017, 5:19 p.m. | #1
On 09/06/17 13:53, Richard Earnshaw wrote:
> 

> This patch has no functional change.  The code used for parsing -mcpu,

> -mtune and -march options is simply moved from arm.c arm-common.c.

> The list of FPU options is also moved.  Subsequent patches will make

> use of this within the driver.

> 

> Some small adjustments are needed as a consequence of moving the

> definitions of the data objects to another object file, in that we

> no-longer have direct access to the size of the object.

> 

> 	* common/config/arm/arm-common.c (arm_initialize_isa): Moved here from

> 	config/arm/arm.c.

> 	(arm_print_hint_for_cpu_option): Likewise.

> 	(arm_print_hint_for_arch_option): Likewise.

> 	(arm_parse_cpu_option_name): Likewise.

> 	(arm_parse_arch_option_name): Likewise.

> 	* config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number

> 	of entries in the all_fpus list.

> 	* config/arm/arm-protos.h (all_architectures, all_cores): Declare.

> 	(arm_parse_cpu_option_name): Declare.

> 	(arm_parse_arch_option_name): Declare.

> 	(arm_parse_option_features): Declare.

> 	(arm_intialize_isa): Declare.

> 	* config/arm/parsecpu.awk (gen_data): Move CPU and architecture

> 	data tables to ...

> 	(gen_comm_data): ... here.  Make definitions non-static.

> 	* config/arm/arm-cpu-data.h: Regenerated.

> 	* config/arm/arm-cpu-cdata.h: Regenerated.


More typo fixes.diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index fd0c616..f44ba1f 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -27,6 +27,8 @@
 #include "common/common-target-def.h"
 #include "opts.h"
 #include "flags.h"
+#include "sbitmap.h"
+#include "diagnostic.h"
 
 /* Set default optimization options.  */
 static const struct default_options arm_option_optimization_table[] =
@@ -187,6 +189,194 @@ arm_target_thumb_only (int argc, const char **argv)
     return NULL;
 }
 
+/* List the permitted CPU option names.  If TARGET is a near miss for an
+   entry, print out the suggested alternative.  */
+static void
+arm_print_hint_for_cpu_option (const char *target,
+			       const cpu_option *list)
+{
+  auto_vec<const char*> candidates;
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
+  char *s;
+  const char *hint = candidates_list_and_hint (target, s, candidates);
+  if (hint)
+    inform (input_location, "valid arguments are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse the base component of a CPU selection in LIST.  Return a
+   pointer to the entry in the architecture table.  OPTNAME is the
+   name of the option we are parsing and can be used if a diagnostic
+   is needed.  */
+const cpu_option *
+arm_parse_cpu_option_name (const cpu_option *list, const char *optname,
+			   const char *target)
+{
+  const cpu_option *entry;
+  const char *end  = strchr (target, '+');
+  size_t len = end ? end - target : strlen (target);
+
+  for (entry = list; entry->common.name != NULL; entry++)
+    {
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
+	return entry;
+    }
+
+  error_at (input_location, "unrecognized %s target: %s", optname, target);
+  arm_print_hint_for_cpu_option (target, list);
+  return NULL;
+}
+
+/* List the permitted architecture option names.  If TARGET is a near
+   miss for an entry, print out the suggested alternative.  */
+static void
+arm_print_hint_for_arch_option (const char *target,
+			       const arch_option *list)
+{
+  auto_vec<const char*> candidates;
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
+  char *s;
+  const char *hint = candidates_list_and_hint (target, s, candidates);
+  if (hint)
+    inform (input_location, "valid arguments are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse the base component of a CPU or architecture selection in
+   LIST.  Return a pointer to the entry in the architecture table.
+   OPTNAME is the name of the option we are parsing and can be used if
+   a diagnostic is needed.  */
+const arch_option *
+arm_parse_arch_option_name (const arch_option *list, const char *optname,
+			    const char *target)
+{
+  const arch_option *entry;
+  const char *end  = strchr (target, '+');
+  size_t len = end ? end - target : strlen (target);
+
+  for (entry = list; entry->common.name != NULL; entry++)
+    {
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
+	return entry;
+    }
+
+  error_at (input_location, "unrecognized %s target: %s", optname, target);
+  arm_print_hint_for_arch_option (target, list);
+  return NULL;
+}
+
+/* Convert a static initializer array of feature bits to sbitmap
+   representation.  */
+void
+arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
+{
+  bitmap_clear (isa);
+  while (*isa_bits != isa_nobit)
+    bitmap_set_bit (isa, *(isa_bits++));
+}
+
+/* OPT isn't a recognized feature.  Print a suitable error message and
+   suggest a possible value.  Always print the list of permitted
+   values.  */
+static void
+arm_unrecognized_feature (const char *opt, size_t len,
+			  const cpu_arch_option *target)
+{
+  char *this_opt = XALLOCAVEC (char, len+1);
+  auto_vec<const char*> candidates;
+
+  strncpy (this_opt, opt, len);
+  this_opt[len] = 0;
+
+  error_at (input_location, "%qs does not support feature %qs", target->name,
+	    this_opt);
+  for (const cpu_arch_extension *list = target->extensions;
+       list->name != NULL;
+       list++)
+    candidates.safe_push (list->name);
+
+  char *s;
+  const char *hint = candidates_list_and_hint (this_opt, s, candidates);
+
+  if (hint)
+    inform (input_location, "valid feature names are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid feature names are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse any feature extensions to add to (or remove from) the
+   permitted ISA selection.  */
+void
+arm_parse_option_features (sbitmap isa, const cpu_arch_option *target,
+			   const char *opts_in)
+{
+  const char *opts = opts_in;
+
+  if (!opts)
+    return;
+
+  if (!target->extensions)
+    {
+      error_at (input_location, "%s does not take any feature options",
+		target->name);
+      return;
+    }
+
+  while (opts)
+    {
+      gcc_assert (*opts == '+');
+      const struct cpu_arch_extension *entry;
+      const char *end = strchr (++opts, '+');
+      size_t len = end ? end - opts : strlen (opts);
+      bool matched = false;
+
+      for (entry = target->extensions;
+	   !matched && entry->name != NULL;
+	   entry++)
+	{
+	  if (strncmp (entry->name, opts, len) == 0
+	      && entry->name[len] == '\0')
+	    {
+	      if (isa)
+		{
+		  const enum isa_feature *f = entry->isa_bits;
+		  if (entry->remove)
+		    {
+		      while (*f != isa_nobit)
+			bitmap_clear_bit (isa, *(f++));
+		    }
+		  else
+		    {
+		      while (*f != isa_nobit)
+			bitmap_set_bit (isa, *(f++));
+		    }
+		}
+	      matched = true;
+	    }
+	}
+
+      if (!matched)
+	arm_unrecognized_feature (opts, len, target);
+
+      opts = end;
+    }
+}
+
 #undef ARM_CPU_NAME_LENGTH
 
 
diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index 3be0b78..9b3b386 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -20,6 +20,2586 @@
    License along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
+static const cpu_arch_extension cpu_opttab_arm9e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm946es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm966es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm968es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm10e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1020e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1022e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_genericv7a[] = {
+  {
+    "simd", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa5[] = {
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa7[] = {
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa8[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa9[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa12[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa15[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa17[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr5[] = {
+  {
+    "nofp.dp", true,
+    { ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr8[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm7[] = {
+  {
+    "nofp.dp", true,
+    { ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm4[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa32[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa35[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa57[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa72[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_exynosm1[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_falkor[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_qdf24xx[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_xgene1[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm33[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+const cpu_option all_cores[] =
+{
+  {
+    {
+      "arm2",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm250",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm3",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm6",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm60",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm600",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm610",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm620",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7d",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7di",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm70",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm700",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm700i",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm710",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm720",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm710c",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7100",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7500",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7500fe",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7m",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm7dm",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm7dmi",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm8",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "arm810",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm1100",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm1110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "fa526",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "fa626",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "arm7tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm7tdmi-s",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm710t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm720t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm740t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm9",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm9tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm920",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm920t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm922t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm940t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "ep9312",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm10tdmi",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5t
+  },
+  {
+    {
+      "arm1020t",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5t
+  },
+  {
+    {
+      "arm9e",
+      cpu_opttab_arm9e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm946e-s",
+      cpu_opttab_arm946es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm966e-s",
+      cpu_opttab_arm966es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm968e-s",
+      cpu_opttab_arm968es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm10e",
+      cpu_opttab_arm10e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm1020e",
+      cpu_opttab_arm1020e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm1022e",
+      cpu_opttab_arm1022e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "xscale",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_bit_xscale,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "iwmmxt",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_iwmmxt
+  },
+  {
+    {
+      "iwmmxt2",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_iwmmxt2
+  },
+  {
+    {
+      "fa606te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fa626te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fmp626",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fa726te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm926ej-s",
+      cpu_opttab_arm926ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5tej
+  },
+  {
+    {
+      "arm1026ej-s",
+      cpu_opttab_arm1026ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5tej
+  },
+  {
+    {
+      "arm1136j-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6j
+  },
+  {
+    {
+      "arm1136jf-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6j
+  },
+  {
+    {
+      "arm1176jz-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6kz
+  },
+  {
+    {
+      "arm1176jzf-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6kz
+  },
+  {
+    {
+      "mpcorenovfp",
+      NULL,
+      {
+        ISA_ARMv6k,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6k
+  },
+  {
+    {
+      "mpcore",
+      NULL,
+      {
+        ISA_ARMv6k,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6k
+  },
+  {
+    {
+      "arm1156t2-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6t2
+  },
+  {
+    {
+      "arm1156t2f-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6t2
+  },
+  {
+    {
+      "cortex-m1",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0plus",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m1.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0plus.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "generic-armv7-a",
+      cpu_opttab_genericv7a,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a5",
+      cpu_opttab_cortexa5,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a7",
+      cpu_opttab_cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a8",
+      cpu_opttab_cortexa8,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a9",
+      cpu_opttab_cortexa9,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a12",
+      cpu_opttab_cortexa12,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a15",
+      cpu_opttab_cortexa15,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a17",
+      cpu_opttab_cortexa17,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-r4",
+      NULL,
+      {
+        ISA_ARMv7r,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r4f",
+      NULL,
+      {
+        ISA_ARMv7r,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r5",
+      cpu_opttab_cortexr5,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r7",
+      cpu_opttab_cortexr7,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r8",
+      cpu_opttab_cortexr8,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-m7",
+      cpu_opttab_cortexm7,
+      {
+        ISA_ARMv7em,
+        ISA_FPv5,ISA_FP_DBL,
+        isa_quirk_no_volatile_ce,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7e_m
+  },
+  {
+    {
+      "cortex-m4",
+      cpu_opttab_cortexm4,
+      {
+        ISA_ARMv7em,
+        ISA_VFPv4,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7e_m
+  },
+  {
+    {
+      "cortex-m3",
+      NULL,
+      {
+        ISA_ARMv7m,
+        isa_quirk_cm3_ldrd,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_m
+  },
+  {
+    {
+      "marvell-pj4",
+      NULL,
+      {
+        ISA_ARMv7a,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a15.cortex-a7",
+      cpu_opttab_cortexa15cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a17.cortex-a7",
+      cpu_opttab_cortexa17cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a32",
+      cpu_opttab_cortexa32,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a35",
+      cpu_opttab_cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a53",
+      cpu_opttab_cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a57",
+      cpu_opttab_cortexa57,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a72",
+      cpu_opttab_cortexa72,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73",
+      cpu_opttab_cortexa73,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "exynos-m1",
+      cpu_opttab_exynosm1,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "falkor",
+      cpu_opttab_falkor,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "qdf24xx",
+      cpu_opttab_qdf24xx,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "xgene1",
+      cpu_opttab_xgene1,
+      {
+        ISA_ARMv8a,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a57.cortex-a53",
+      cpu_opttab_cortexa57cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a72.cortex-a53",
+      cpu_opttab_cortexa72cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a35",
+      cpu_opttab_cortexa73cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a53",
+      cpu_opttab_cortexa73cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-m23",
+      NULL,
+      {
+        ISA_ARMv8m_base,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_base
+  },
+  {
+    {
+      "cortex-m33",
+      cpu_opttab_cortexm33,
+      {
+        ISA_ARMv8m_main,
+        isa_bit_ARMv7em,
+        ISA_FPv5,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_main
+  },
+  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
+};
+static const struct cpu_arch_extension arch_opttab_armv5e[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv5te[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6j[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6k[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6z[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
+  {
+    "fp.sp", false,
+    { ISA_VFPv3, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "idiv", false,
+    { isa_bit_adiv, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "noidiv", true,
+    { isa_bit_adiv, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
+  {
+    "fp", false,
+    { ISA_VFPv4, isa_nobit }
+  },
+  {
+    "fpv5", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
+  {
+    "crc", false,
+    { isa_bit_crc32, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "fp16", false,
+    { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
+  {
+    "dsp", false,
+    { isa_bit_ARMv7em, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+const arch_option all_architectures[] =
+{
+  {
+    "armv2",
+    NULL,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
+  },
+  {
+    "armv2a",
+    NULL,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
+  },
+  {
+    "armv3",
+    NULL,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    "3", BASE_ARCH_3,
+    TARGET_CPU_arm6,
+  },
+  {
+    "armv3m",
+    NULL,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    "3M", BASE_ARCH_3M,
+    TARGET_CPU_arm7m,
+  },
+  {
+    "armv4",
+    NULL,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    "4", BASE_ARCH_4,
+    TARGET_CPU_arm7tdmi,
+  },
+  {
+    "armv4t",
+    NULL,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    "4T", BASE_ARCH_4T,
+    TARGET_CPU_arm7tdmi,
+  },
+  {
+    "armv5",
+    NULL,
+    {
+      ISA_ARMv5,
+      isa_nobit
+    },
+    "5", BASE_ARCH_5,
+    TARGET_CPU_arm10tdmi,
+  },
+  {
+    "armv5t",
+    NULL,
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+    "5T", BASE_ARCH_5T,
+    TARGET_CPU_arm10tdmi,
+  },
+  {
+    "armv5e",
+    arch_opttab_armv5e,
+    {
+      ISA_ARMv5e,
+      isa_nobit
+    },
+    "5E", BASE_ARCH_5E,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv5te",
+    arch_opttab_armv5te,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv5tej",
+    arch_opttab_armv5tej,
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+    "5TEJ", BASE_ARCH_5TEJ,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv6",
+    arch_opttab_armv6,
+    {
+      ISA_ARMv6,
+      isa_nobit
+    },
+    "6", BASE_ARCH_6,
+    TARGET_CPU_arm1136js,
+  },
+  {
+    "armv6j",
+    arch_opttab_armv6j,
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+    "6J", BASE_ARCH_6J,
+    TARGET_CPU_arm1136js,
+  },
+  {
+    "armv6k",
+    arch_opttab_armv6k,
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+    "6K", BASE_ARCH_6K,
+    TARGET_CPU_mpcore,
+  },
+  {
+    "armv6z",
+    arch_opttab_armv6z,
+    {
+      ISA_ARMv6z,
+      isa_nobit
+    },
+    "6Z", BASE_ARCH_6Z,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6kz",
+    arch_opttab_armv6kz,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6zk",
+    arch_opttab_armv6zk,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6t2",
+    arch_opttab_armv6t2,
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+    "6T2", BASE_ARCH_6T2,
+    TARGET_CPU_arm1156t2s,
+  },
+  {
+    "armv6-m",
+    NULL,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
+  },
+  {
+    "armv6s-m",
+    NULL,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
+  },
+  {
+    "armv7",
+    arch_opttab_armv7,
+    {
+      ISA_ARMv7,
+      isa_nobit
+    },
+    "7", BASE_ARCH_7,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7-a",
+    arch_opttab_armv7_a,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7ve",
+    arch_opttab_armv7ve,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7-r",
+    arch_opttab_armv7_r,
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+    "7R", BASE_ARCH_7R,
+    TARGET_CPU_cortexr4,
+  },
+  {
+    "armv7-m",
+    NULL,
+    {
+      ISA_ARMv7m,
+      isa_nobit
+    },
+    "7M", BASE_ARCH_7M,
+    TARGET_CPU_cortexm3,
+  },
+  {
+    "armv7e-m",
+    arch_opttab_armv7e_m,
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+    "7EM", BASE_ARCH_7EM,
+    TARGET_CPU_cortexm4,
+  },
+  {
+    "armv8-a",
+    arch_opttab_armv8_a,
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8.1-a",
+    arch_opttab_armv8_1_a,
+    {
+      ISA_ARMv8_1a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8.2-a",
+    arch_opttab_armv8_2_a,
+    {
+      ISA_ARMv8_2a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8-m.base",
+    NULL,
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+    "8M_BASE", BASE_ARCH_8M_BASE,
+    TARGET_CPU_cortexm23,
+  },
+  {
+    "armv8-m.main",
+    arch_opttab_armv8_m_main,
+    {
+      ISA_ARMv8m_main,
+      isa_nobit
+    },
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    TARGET_CPU_cortexm7,
+  },
+  {
+    "iwmmxt",
+    NULL,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt,
+  },
+  {
+    "iwmmxt2",
+    NULL,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt2,
+  },
+  {{NULL, NULL, {isa_nobit}},
+   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}
+};
+
+const arm_fpu_desc all_fpus[] =
+{
+  {
+    "vfp",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv2",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-fp16",
+    {
+      ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16-fp16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd",
+    {
+      ISA_VFPv3,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd-fp16",
+    {
+      ISA_VFPv3,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "neon",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv3",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp16",
+    {
+      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4",
+    {
+      ISA_VFPv4,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv4",
+    {
+      ISA_VFPv4,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4-d16",
+    {
+      ISA_VFPv4,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fpv4-sp-d16",
+    {
+      ISA_VFPv4,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-sp-d16",
+    {
+      ISA_FPv5,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-d16",
+    {
+      ISA_FPv5,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "crypto-neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_CRYPTO,
+      isa_nobit
+    }
+  },
+  {
+    "vfp3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+};
 static const struct arm_arch_core_flag arm_arch_core_flags[] =
 {
   {
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index 0e45b23..c2a18e3 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -20,1676 +20,6 @@
    License along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-static const cpu_arch_extension cpu_opttab_arm9e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm946es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm966es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm968es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm10e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1020e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1022e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_genericv7a[] = {
-  {
-    "simd", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa5[] = {
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa7[] = {
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa8[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa9[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa12[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa15[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa17[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr5[] = {
-  {
-    "nofp.dp", true,
-    { ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr8[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm7[] = {
-  {
-    "nofp.dp", true,
-    { ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm4[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa32[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa35[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa57[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa72[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_exynosm1[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_falkor[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_qdf24xx[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_xgene1[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm33[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_option all_cores[] =
-{
-  {
-    {
-      "arm2",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm250",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm3",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm6",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm60",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm600",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm610",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm620",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7d",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7di",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm70",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm700",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm700i",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm710",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm720",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm710c",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7100",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7500",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7500fe",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7m",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm7dm",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm7dmi",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm8",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "arm810",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm110",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm1100",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm1110",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "fa526",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "fa626",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "arm7tdmi",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm7tdmi-s",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm710t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm720t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm740t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm9",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm9tdmi",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm920",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm920t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm922t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm940t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "ep9312",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm10tdmi",
-      NULL,
-      {
-        ISA_ARMv5t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5t
-  },
-  {
-    {
-      "arm1020t",
-      NULL,
-      {
-        ISA_ARMv5t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5t
-  },
-  {
-    {
-      "arm9e",
-      cpu_opttab_arm9e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm946e-s",
-      cpu_opttab_arm946es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm966e-s",
-      cpu_opttab_arm966es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm968e-s",
-      cpu_opttab_arm968es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm10e",
-      cpu_opttab_arm10e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm1020e",
-      cpu_opttab_arm1020e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm1022e",
-      cpu_opttab_arm1022e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "xscale",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_bit_xscale,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "iwmmxt",
-      NULL,
-      {
-        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_iwmmxt
-  },
-  {
-    {
-      "iwmmxt2",
-      NULL,
-      {
-        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_iwmmxt2
-  },
-  {
-    {
-      "fa606te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fa626te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fmp626",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fa726te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm926ej-s",
-      cpu_opttab_arm926ejs,
-      {
-        ISA_ARMv5tej,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5tej
-  },
-  {
-    {
-      "arm1026ej-s",
-      cpu_opttab_arm1026ejs,
-      {
-        ISA_ARMv5tej,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5tej
-  },
-  {
-    {
-      "arm1136j-s",
-      NULL,
-      {
-        ISA_ARMv6j,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6j
-  },
-  {
-    {
-      "arm1136jf-s",
-      NULL,
-      {
-        ISA_ARMv6j,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6j
-  },
-  {
-    {
-      "arm1176jz-s",
-      NULL,
-      {
-        ISA_ARMv6kz,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6kz
-  },
-  {
-    {
-      "arm1176jzf-s",
-      NULL,
-      {
-        ISA_ARMv6kz,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6kz
-  },
-  {
-    {
-      "mpcorenovfp",
-      NULL,
-      {
-        ISA_ARMv6k,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6k
-  },
-  {
-    {
-      "mpcore",
-      NULL,
-      {
-        ISA_ARMv6k,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6k
-  },
-  {
-    {
-      "arm1156t2-s",
-      NULL,
-      {
-        ISA_ARMv6t2,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6t2
-  },
-  {
-    {
-      "arm1156t2f-s",
-      NULL,
-      {
-        ISA_ARMv6t2,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6t2
-  },
-  {
-    {
-      "cortex-m1",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0plus",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m1.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0plus.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "generic-armv7-a",
-      cpu_opttab_genericv7a,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a5",
-      cpu_opttab_cortexa5,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a7",
-      cpu_opttab_cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a8",
-      cpu_opttab_cortexa8,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a9",
-      cpu_opttab_cortexa9,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a12",
-      cpu_opttab_cortexa12,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a15",
-      cpu_opttab_cortexa15,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a17",
-      cpu_opttab_cortexa17,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-r4",
-      NULL,
-      {
-        ISA_ARMv7r,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r4f",
-      NULL,
-      {
-        ISA_ARMv7r,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r5",
-      cpu_opttab_cortexr5,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r7",
-      cpu_opttab_cortexr7,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r8",
-      cpu_opttab_cortexr8,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-m7",
-      cpu_opttab_cortexm7,
-      {
-        ISA_ARMv7em,
-        ISA_FPv5,ISA_FP_DBL,
-        isa_quirk_no_volatile_ce,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7e_m
-  },
-  {
-    {
-      "cortex-m4",
-      cpu_opttab_cortexm4,
-      {
-        ISA_ARMv7em,
-        ISA_VFPv4,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7e_m
-  },
-  {
-    {
-      "cortex-m3",
-      NULL,
-      {
-        ISA_ARMv7m,
-        isa_quirk_cm3_ldrd,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_m
-  },
-  {
-    {
-      "marvell-pj4",
-      NULL,
-      {
-        ISA_ARMv7a,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a15.cortex-a7",
-      cpu_opttab_cortexa15cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a17.cortex-a7",
-      cpu_opttab_cortexa17cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a32",
-      cpu_opttab_cortexa32,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a35",
-      cpu_opttab_cortexa35,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a53",
-      cpu_opttab_cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a57",
-      cpu_opttab_cortexa57,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a72",
-      cpu_opttab_cortexa72,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73",
-      cpu_opttab_cortexa73,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "exynos-m1",
-      cpu_opttab_exynosm1,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "falkor",
-      cpu_opttab_falkor,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "qdf24xx",
-      cpu_opttab_qdf24xx,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "xgene1",
-      cpu_opttab_xgene1,
-      {
-        ISA_ARMv8a,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a57.cortex-a53",
-      cpu_opttab_cortexa57cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a72.cortex-a53",
-      cpu_opttab_cortexa72cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73.cortex-a35",
-      cpu_opttab_cortexa73cortexa35,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73.cortex-a53",
-      cpu_opttab_cortexa73cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-m23",
-      NULL,
-      {
-        ISA_ARMv8m_base,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_m_base
-  },
-  {
-    {
-      "cortex-m33",
-      cpu_opttab_cortexm33,
-      {
-        ISA_ARMv8m_main,
-        isa_bit_ARMv7em,
-        ISA_FPv5,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_m_main
-  },
-  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
-};
 static const cpu_tune all_tunes[] =
 {
   { /* arm2.  */
@@ -2244,913 +574,3 @@ static const cpu_tune all_tunes[] =
   },
   {TARGET_CPU_arm_none, 0, NULL}
 };
-static const struct cpu_arch_extension arch_opttab_armv5e[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv5te[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6j[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6k[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6z[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7[] = {
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
-  {
-    "fp.sp", false,
-    { ISA_VFPv3, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "idiv", false,
-    { isa_bit_adiv, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "noidiv", true,
-    { isa_bit_adiv, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
-  {
-    "fp", false,
-    { ISA_VFPv4, isa_nobit }
-  },
-  {
-    "fpv5", false,
-    { ISA_FPv5, isa_nobit }
-  },
-  {
-    "fp.dp", false,
-    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
-  {
-    "crc", false,
-    { isa_bit_crc32, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "fp16", false,
-    { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
-  {
-    "dsp", false,
-    { isa_bit_ARMv7em, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_FPv5, isa_nobit }
-  },
-  {
-    "fp.dp", false,
-    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct arch_option all_architectures[] =
-{
-  {
-    "armv2",
-    NULL,
-    {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
-    },
-    "2", BASE_ARCH_2,
-    TARGET_CPU_arm2,
-  },
-  {
-    "armv2a",
-    NULL,
-    {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
-    },
-    "2", BASE_ARCH_2,
-    TARGET_CPU_arm2,
-  },
-  {
-    "armv3",
-    NULL,
-    {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
-    },
-    "3", BASE_ARCH_3,
-    TARGET_CPU_arm6,
-  },
-  {
-    "armv3m",
-    NULL,
-    {
-      ISA_ARMv3m,isa_bit_mode26,
-      isa_nobit
-    },
-    "3M", BASE_ARCH_3M,
-    TARGET_CPU_arm7m,
-  },
-  {
-    "armv4",
-    NULL,
-    {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
-    },
-    "4", BASE_ARCH_4,
-    TARGET_CPU_arm7tdmi,
-  },
-  {
-    "armv4t",
-    NULL,
-    {
-      ISA_ARMv4t,
-      isa_nobit
-    },
-    "4T", BASE_ARCH_4T,
-    TARGET_CPU_arm7tdmi,
-  },
-  {
-    "armv5",
-    NULL,
-    {
-      ISA_ARMv5,
-      isa_nobit
-    },
-    "5", BASE_ARCH_5,
-    TARGET_CPU_arm10tdmi,
-  },
-  {
-    "armv5t",
-    NULL,
-    {
-      ISA_ARMv5t,
-      isa_nobit
-    },
-    "5T", BASE_ARCH_5T,
-    TARGET_CPU_arm10tdmi,
-  },
-  {
-    "armv5e",
-    arch_opttab_armv5e,
-    {
-      ISA_ARMv5e,
-      isa_nobit
-    },
-    "5E", BASE_ARCH_5E,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv5te",
-    arch_opttab_armv5te,
-    {
-      ISA_ARMv5te,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv5tej",
-    arch_opttab_armv5tej,
-    {
-      ISA_ARMv5tej,
-      isa_nobit
-    },
-    "5TEJ", BASE_ARCH_5TEJ,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv6",
-    arch_opttab_armv6,
-    {
-      ISA_ARMv6,
-      isa_nobit
-    },
-    "6", BASE_ARCH_6,
-    TARGET_CPU_arm1136js,
-  },
-  {
-    "armv6j",
-    arch_opttab_armv6j,
-    {
-      ISA_ARMv6j,
-      isa_nobit
-    },
-    "6J", BASE_ARCH_6J,
-    TARGET_CPU_arm1136js,
-  },
-  {
-    "armv6k",
-    arch_opttab_armv6k,
-    {
-      ISA_ARMv6k,
-      isa_nobit
-    },
-    "6K", BASE_ARCH_6K,
-    TARGET_CPU_mpcore,
-  },
-  {
-    "armv6z",
-    arch_opttab_armv6z,
-    {
-      ISA_ARMv6z,
-      isa_nobit
-    },
-    "6Z", BASE_ARCH_6Z,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6kz",
-    arch_opttab_armv6kz,
-    {
-      ISA_ARMv6kz,
-      isa_nobit
-    },
-    "6KZ", BASE_ARCH_6KZ,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6zk",
-    arch_opttab_armv6zk,
-    {
-      ISA_ARMv6kz,
-      isa_nobit
-    },
-    "6KZ", BASE_ARCH_6KZ,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6t2",
-    arch_opttab_armv6t2,
-    {
-      ISA_ARMv6t2,
-      isa_nobit
-    },
-    "6T2", BASE_ARCH_6T2,
-    TARGET_CPU_arm1156t2s,
-  },
-  {
-    "armv6-m",
-    NULL,
-    {
-      ISA_ARMv6m,
-      isa_nobit
-    },
-    "6M", BASE_ARCH_6M,
-    TARGET_CPU_cortexm1,
-  },
-  {
-    "armv6s-m",
-    NULL,
-    {
-      ISA_ARMv6m,
-      isa_nobit
-    },
-    "6M", BASE_ARCH_6M,
-    TARGET_CPU_cortexm1,
-  },
-  {
-    "armv7",
-    arch_opttab_armv7,
-    {
-      ISA_ARMv7,
-      isa_nobit
-    },
-    "7", BASE_ARCH_7,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7-a",
-    arch_opttab_armv7_a,
-    {
-      ISA_ARMv7a,
-      isa_nobit
-    },
-    "7A", BASE_ARCH_7A,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7ve",
-    arch_opttab_armv7ve,
-    {
-      ISA_ARMv7ve,
-      isa_nobit
-    },
-    "7A", BASE_ARCH_7A,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7-r",
-    arch_opttab_armv7_r,
-    {
-      ISA_ARMv7r,
-      isa_nobit
-    },
-    "7R", BASE_ARCH_7R,
-    TARGET_CPU_cortexr4,
-  },
-  {
-    "armv7-m",
-    NULL,
-    {
-      ISA_ARMv7m,
-      isa_nobit
-    },
-    "7M", BASE_ARCH_7M,
-    TARGET_CPU_cortexm3,
-  },
-  {
-    "armv7e-m",
-    arch_opttab_armv7e_m,
-    {
-      ISA_ARMv7em,
-      isa_nobit
-    },
-    "7EM", BASE_ARCH_7EM,
-    TARGET_CPU_cortexm4,
-  },
-  {
-    "armv8-a",
-    arch_opttab_armv8_a,
-    {
-      ISA_ARMv8a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8.1-a",
-    arch_opttab_armv8_1_a,
-    {
-      ISA_ARMv8_1a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8.2-a",
-    arch_opttab_armv8_2_a,
-    {
-      ISA_ARMv8_2a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8-m.base",
-    NULL,
-    {
-      ISA_ARMv8m_base,
-      isa_nobit
-    },
-    "8M_BASE", BASE_ARCH_8M_BASE,
-    TARGET_CPU_cortexm23,
-  },
-  {
-    "armv8-m.main",
-    arch_opttab_armv8_m_main,
-    {
-      ISA_ARMv8m_main,
-      isa_nobit
-    },
-    "8M_MAIN", BASE_ARCH_8M_MAIN,
-    TARGET_CPU_cortexm7,
-  },
-  {
-    "iwmmxt",
-    NULL,
-    {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_iwmmxt,
-  },
-  {
-    "iwmmxt2",
-    NULL,
-    {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_iwmmxt2,
-  },
-  {{NULL, NULL, {isa_nobit}},
-   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}
-};
-
-const struct arm_fpu_desc all_fpus[] =
-{
-  {
-    "vfp",
-    {
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv2",
-    {
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3",
-    {
-      ISA_VFPv3,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-fp16",
-    {
-      ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-d16",
-    {
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-d16-fp16",
-    {
-      ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3xd",
-    {
-      ISA_VFPv3,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3xd-fp16",
-    {
-      ISA_VFPv3,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "neon",
-    {
-      ISA_VFPv3,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "neon-vfpv3",
-    {
-      ISA_VFPv3,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "neon-fp16",
-    {
-      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv4",
-    {
-      ISA_VFPv4,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "neon-vfpv4",
-    {
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv4-d16",
-    {
-      ISA_VFPv4,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "fpv4-sp-d16",
-    {
-      ISA_VFPv4,
-      isa_nobit
-    }
-  },
-  {
-    "fpv5-sp-d16",
-    {
-      ISA_FPv5,
-      isa_nobit
-    }
-  },
-  {
-    "fpv5-d16",
-    {
-      ISA_FPv5,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "neon-fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "crypto-neon-fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_CRYPTO,
-      isa_nobit
-    }
-  },
-  {
-    "vfp3",
-    {
-      ISA_VFPv3,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-};
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index ada2503..f30b81e 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -513,4 +513,16 @@ struct cpu_option
   enum arch_type arch;
 };
 
+extern const arch_option all_architectures[];
+extern const cpu_option all_cores[];
+
+const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *,
+					     const char *);
+const arch_option *arm_parse_arch_option_name (const arch_option *,
+					       const char *, const char *);
+void arm_parse_option_features (sbitmap, const cpu_arch_option *,
+				const char *);
+
+void arm_initialize_isa (sbitmap, const enum isa_feature *);
+
 #endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2b1d5e2..4abb31f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3046,194 +3046,6 @@ arm_option_override_internal (struct gcc_options *opts,
 #endif
 }
 
-/* Convert a static initializer array of feature bits to sbitmap
-   representation.  */
-static void
-arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
-{
-  bitmap_clear (isa);
-  while (*isa_bits != isa_nobit)
-    bitmap_set_bit (isa, *(isa_bits++));
-}
-
-/* List the permitted CPU option names.  If TARGET is a near miss for an
-   entry, print out the suggested alternative.  */
-static void
-arm_print_hint_for_cpu_option (const char *target,
-			       const cpu_option *list)
-{
-  auto_vec<const char*> candidates;
-  for (; list->common.name != NULL; list++)
-    candidates.safe_push (list->common.name);
-  char *s;
-  const char *hint = candidates_list_and_hint (target, s, candidates);
-  if (hint)
-    inform (input_location, "valid arguments are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid arguments are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse the base component of a CPU selection in LIST.  Return a
-   pointer to the entry in the architecture table.  OPTNAME is the
-   name of the option we are parsing and can be used if a diagnostic
-   is needed.  */
-static const cpu_option *
-arm_parse_cpu_option_name (const cpu_option *list, const char *optname,
-		       const char *target)
-{
-  const cpu_option *entry;
-  const char *end  = strchr (target, '+');
-  size_t len = end ? end - target : strlen (target);
-
-  for (entry = list; entry->common.name != NULL; entry++)
-    {
-      if (strncmp (entry->common.name, target, len) == 0
-	  && entry->common.name[len] == '\0')
-	return entry;
-    }
-
-  error_at (input_location, "unrecognized %s target: %s", optname, target);
-  arm_print_hint_for_cpu_option (target, list);
-  return NULL;
-}
-
-/* List the permitted architecture option names.  If TARGET is a near
-   miss for an entry, print out the suggested alternative.  */
-static void
-arm_print_hint_for_arch_option (const char *target,
-			       const arch_option *list)
-{
-  auto_vec<const char*> candidates;
-  for (; list->common.name != NULL; list++)
-    candidates.safe_push (list->common.name);
-  char *s;
-  const char *hint = candidates_list_and_hint (target, s, candidates);
-  if (hint)
-    inform (input_location, "valid arguments are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid arguments are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse the base component of a CPU or architecture selection in
-   LIST.  Return a pointer to the entry in the architecture table.
-   OPTNAME is the name of the option we are parsing and can be used if
-   a diagnostic is needed.  */
-static const arch_option *
-arm_parse_arch_option_name (const arch_option *list, const char *optname,
-			    const char *target)
-{
-  const arch_option *entry;
-  const char *end  = strchr (target, '+');
-  size_t len = end ? end - target : strlen (target);
-
-  for (entry = list; entry->common.name != NULL; entry++)
-    {
-      if (strncmp (entry->common.name, target, len) == 0
-	  && entry->common.name[len] == '\0')
-	return entry;
-    }
-
-  error_at (input_location, "unrecognized %s target: %s", optname, target);
-  arm_print_hint_for_arch_option (target, list);
-  return NULL;
-}
-
-/* OPT isn't a recognized feature.  Print a suitable error message and
-   suggest a possible value.  Always print the list of permitted
-   values.  */
-static void
-arm_unrecognized_feature (const char *opt, size_t len,
-			  const cpu_arch_option *target)
-{
-  char *this_opt = XALLOCAVEC (char, len+1);
-  auto_vec<const char*> candidates;
-
-  strncpy (this_opt, opt, len);
-  this_opt[len] = 0;
-
-  error_at (input_location, "%qs does not support feature %qs", target->name,
-	    this_opt);
-  for (const cpu_arch_extension *list = target->extensions;
-       list->name != NULL;
-       list++)
-    candidates.safe_push (list->name);
-
-  char *s;
-  const char *hint = candidates_list_and_hint (this_opt, s, candidates);
-
-  if (hint)
-    inform (input_location, "valid feature names are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid feature names are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse any feature extensions to add to (or remove from) the
-   permitted ISA selection.  */
-static void
-arm_parse_option_features (sbitmap isa, const cpu_arch_option *target,
-			   const char *opts_in)
-{
-  const char *opts = opts_in;
-
-  if (!opts)
-    return;
-
-  if (!target->extensions)
-    {
-      error_at (input_location, "%s does not take any feature options",
-		target->name);
-      return;
-    }
-
-  while (opts)
-    {
-      gcc_assert (*opts == '+');
-      const struct cpu_arch_extension *entry;
-      const char *end = strchr (++opts, '+');
-      size_t len = end ? end - opts : strlen (opts);
-      bool matched = false;
-
-      for (entry = target->extensions;
-	   !matched && entry->name != NULL;
-	   entry++)
-	{
-	  if (strncmp (entry->name, opts, len) == 0
-	      && entry->name[len] == '\0')
-	    {
-	      if (isa)
-		{
-		  const enum isa_feature *f = entry->isa_bits;
-		  if (entry->remove)
-		    {
-		      while (*f != isa_nobit)
-			bitmap_clear_bit (isa, *(f++));
-		    }
-		  else
-		    {
-		      while (*f != isa_nobit)
-			bitmap_set_bit (isa, *(f++));
-		    }
-		}
-	      matched = true;
-	    }
-	}
-
-      if (!matched)
-	arm_unrecognized_feature (opts, len, target);
-
-      opts = end;
-    }
-}
-
 static sbitmap isa_all_fpubits;
 static sbitmap isa_quirkbits;
 
@@ -30902,7 +30714,7 @@ arm_identify_fpu_from_isa (sbitmap isa)
   if (bitmap_empty_p (fpubits))
     return "softvfp";
 
-  for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++)
+  for (unsigned int i = 0; i < TARGET_FPU_auto; i++)
     {
       arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits);
       if (bitmap_equal_p (fpubits, cand_fpubits))
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index 57565bd..70b8938 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -128,6 +128,39 @@ function gen_headers () {
 function gen_data () {
     boilerplate("C")
 
+    print "static const cpu_tune all_tunes[] ="
+    print "{"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  { /* " cpus[n] ".  */"
+	# scheduler
+	if (cpus[n] in cpu_tune_for) {
+	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
+		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
+		      " for CPU " cpus[n])
+	    }
+	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
+	} else {
+	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
+	}
+	# tune_flags
+	if (cpus[n] in cpu_tune_flags) {
+	    print "    (" cpu_tune_flags[cpus[n]] "),"
+	} else print "    0,"
+	# tune
+	print "    &arm_" cpu_cost[cpus[n]] "_tune"
+	print "  },"
+    }
+    print "  {TARGET_CPU_arm_none, 0, NULL}"
+    print "};"
+    
+}
+
+function gen_comm_data () {
+    boilerplate("C")
+
     ncpus = split (cpu_list, cpus)
 
     for (n = 1; n <= ncpus; n++) {
@@ -147,7 +180,7 @@ function gen_data () {
 	}
     }
 
-    print "static const cpu_option all_cores[] ="
+    print "const cpu_option all_cores[] ="
     print "{"
 
     for (n = 1; n <= ncpus; n++) {
@@ -188,32 +221,6 @@ function gen_data () {
     print "  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}"
     print "};"
 
-    print "static const cpu_tune all_tunes[] ="
-    print "{"
-
-    for (n = 1; n <= ncpus; n++) {
-	print "  { /* " cpus[n] ".  */"
-	# scheduler
-	if (cpus[n] in cpu_tune_for) {
-	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
-		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
-		      " for CPU " cpus[n])
-	    }
-	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
-	} else {
-	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
-	}
-	# tune_flags
-	if (cpus[n] in cpu_tune_flags) {
-	    print "    (" cpu_tune_flags[cpus[n]] "),"
-	} else print "    0,"
-	# tune
-	print "    &arm_" cpu_cost[cpus[n]] "_tune"
-	print "  },"
-    }
-    print "  {TARGET_CPU_arm_none, 0, NULL}"
-    print "};"
-    
     narchs = split (arch_list, archs)
 
     for (n = 1; n <= narchs; n++) {
@@ -233,7 +240,7 @@ function gen_data () {
 	}
     }
 
-    print "static const struct arch_option all_architectures[] ="
+    print "const arch_option all_architectures[] ="
     print "{"
 
     for (n = 1; n <= narchs; n++) {
@@ -265,7 +272,7 @@ function gen_data () {
     print "   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}"
     print "};\n"
 
-    print "const struct arm_fpu_desc all_fpus[] ="
+    print "const arm_fpu_desc all_fpus[] ="
     print "{"
 
     nfpus = split (fpu_list, fpus)
@@ -281,10 +288,6 @@ function gen_data () {
     }
 
     print "};"
-}
-
-function gen_comm_data () {
-    boilerplate("C")
 
     print "static const struct arm_arch_core_flag arm_arch_core_flags[] ="
     print "{"

Patch hide | download patch | download mbox

diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index fd0c616..553123c 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -27,6 +27,8 @@ 
 #include "common/common-target-def.h"
 #include "opts.h"
 #include "flags.h"
+#include "sbitmap.h"
+#include "diagnostic.h"
 
 /* Set default optimization options.  */
 static const struct default_options arm_option_optimization_table[] =
@@ -187,6 +189,194 @@  arm_target_thumb_only (int argc, const char **argv)
     return NULL;
 }
 
+/* List the premitted CPU option names.  If TARGET is a near miss for an
+   entry, print out the suggested alternative.  */
+static void
+arm_print_hint_for_cpu_option (const char *target,
+			       const cpu_option *list)
+{
+  auto_vec<const char*> candidates;
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
+  char *s;
+  const char *hint = candidates_list_and_hint (target, s, candidates);
+  if (hint)
+    inform (input_location, "valid arguments are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse the base component of a CPU selection in LIST.  Return a
+   pointer to the entry in the architecture table.  OPTNAME is the
+   name of the option we are parsing and can be used if a diagnostic
+   is needed.  */
+const cpu_option *
+arm_parse_cpu_option_name (const cpu_option *list, const char *optname,
+			   const char *target)
+{
+  const cpu_option *entry;
+  const char *end  = strchr (target, '+');
+  size_t len = end ? end - target : strlen (target);
+
+  for (entry = list; entry->common.name != NULL; entry++)
+    {
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
+	return entry;
+    }
+
+  error_at (input_location, "unrecognized %s target: %s", optname, target);
+  arm_print_hint_for_cpu_option (target, list);
+  return NULL;
+}
+
+/* List the premitted architecture option names.  If TARGET is a near
+   miss for an entry, print out the suggested alternative.  */
+static void
+arm_print_hint_for_arch_option (const char *target,
+			       const arch_option *list)
+{
+  auto_vec<const char*> candidates;
+  for (; list->common.name != NULL; list++)
+    candidates.safe_push (list->common.name);
+  char *s;
+  const char *hint = candidates_list_and_hint (target, s, candidates);
+  if (hint)
+    inform (input_location, "valid arguments are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid arguments are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse the base component of a CPU or architecture selection in
+   LIST.  Return a pointer to the entry in the architecture table.
+   OPTNAME is the name of the option we are parsing and can be used if
+   a diagnostic is needed.  */
+const arch_option *
+arm_parse_arch_option_name (const arch_option *list, const char *optname,
+			    const char *target)
+{
+  const arch_option *entry;
+  const char *end  = strchr (target, '+');
+  size_t len = end ? end - target : strlen (target);
+
+  for (entry = list; entry->common.name != NULL; entry++)
+    {
+      if (strncmp (entry->common.name, target, len) == 0
+	  && entry->common.name[len] == '\0')
+	return entry;
+    }
+
+  error_at (input_location, "unrecognized %s target: %s", optname, target);
+  arm_print_hint_for_arch_option (target, list);
+  return NULL;
+}
+
+/* Convert a static initializer array of feature bits to sbitmap
+   representation.  */
+void
+arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
+{
+  bitmap_clear (isa);
+  while (*isa_bits != isa_nobit)
+    bitmap_set_bit (isa, *(isa_bits++));
+}
+
+/* OPT isn't a recognized feature.  Print a suitable error message and
+   suggest a possible value.  Always print the list of premitted
+   values.  */
+static void
+arm_unrecognized_feature (const char *opt, size_t len,
+			  const cpu_arch_option *target)
+{
+  char *this_opt = XALLOCAVEC (char, len+1);
+  auto_vec<const char*> candidates;
+
+  strncpy (this_opt, opt, len);
+  this_opt[len] = 0;
+
+  error_at (input_location, "%qs does not support feature %qs", target->name,
+	    this_opt);
+  for (const cpu_arch_extension *list = target->extensions;
+       list->name != NULL;
+       list++)
+    candidates.safe_push (list->name);
+
+  char *s;
+  const char *hint = candidates_list_and_hint (this_opt, s, candidates);
+
+  if (hint)
+    inform (input_location, "valid feature names are: %s; did you mean %qs?",
+	    s, hint);
+  else
+    inform (input_location, "valid feature names are: %s", s);
+
+  XDELETEVEC (s);
+}
+
+/* Parse any feature extensions to add to (or remove from) the
+   permitted ISA selection.  */
+void
+arm_parse_option_features (sbitmap isa, const cpu_arch_option *target,
+			   const char *opts_in)
+{
+  const char *opts = opts_in;
+
+  if (!opts)
+    return;
+
+  if (!target->extensions)
+    {
+      error_at (input_location, "%s does not take any feature options",
+		target->name);
+      return;
+    }
+
+  while (opts)
+    {
+      gcc_assert (*opts == '+');
+      const struct cpu_arch_extension *entry;
+      const char *end = strchr (++opts, '+');
+      size_t len = end ? end - opts : strlen (opts);
+      bool matched = false;
+
+      for (entry = target->extensions;
+	   !matched && entry->name != NULL;
+	   entry++)
+	{
+	  if (strncmp (entry->name, opts, len) == 0
+	      && entry->name[len] == '\0')
+	    {
+	      if (isa)
+		{
+		  const enum isa_feature *f = entry->isa_bits;
+		  if (entry->remove)
+		    {
+		      while (*f != isa_nobit)
+			bitmap_clear_bit (isa, *(f++));
+		    }
+		  else
+		    {
+		      while (*f != isa_nobit)
+			bitmap_set_bit (isa, *(f++));
+		    }
+		}
+	      matched = true;
+	    }
+	}
+
+      if (!matched)
+	arm_unrecognized_feature (opts, len, target);
+
+      opts = end;
+    }
+}
+
 #undef ARM_CPU_NAME_LENGTH
 
 
diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h
index 3be0b78..9b3b386 100644
--- a/gcc/config/arm/arm-cpu-cdata.h
+++ b/gcc/config/arm/arm-cpu-cdata.h
@@ -20,6 +20,2586 @@ 
    License along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
+static const cpu_arch_extension cpu_opttab_arm9e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm946es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm966es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm968es[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm10e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1020e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1022e[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_genericv7a[] = {
+  {
+    "simd", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa5[] = {
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa7[] = {
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa8[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa9[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa12[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa15[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa17[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr5[] = {
+  {
+    "nofp.dp", true,
+    { ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexr8[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm7[] = {
+  {
+    "nofp.dp", true,
+    { ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm4[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa32[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa35[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa57[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa72[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_exynosm1[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_falkor[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_qdf24xx[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_xgene1[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const cpu_arch_extension cpu_opttab_cortexm33[] = {
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+const cpu_option all_cores[] =
+{
+  {
+    {
+      "arm2",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm250",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm3",
+      NULL,
+      {
+        ISA_ARMv2,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv2
+  },
+  {
+    {
+      "arm6",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm60",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm600",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm610",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm620",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7d",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7di",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm70",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm700",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm700i",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm710",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm720",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm710c",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7100",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7500",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7500fe",
+      NULL,
+      {
+        ISA_ARMv3,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3
+  },
+  {
+    {
+      "arm7m",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm7dm",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm7dmi",
+      NULL,
+      {
+        ISA_ARMv3m,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv3m
+  },
+  {
+    {
+      "arm8",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "arm810",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm1100",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "strongarm1110",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "fa526",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "fa626",
+      NULL,
+      {
+        ISA_ARMv4,isa_bit_mode26,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4
+  },
+  {
+    {
+      "arm7tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm7tdmi-s",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm710t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm720t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm740t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm9",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm9tdmi",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm920",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm920t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm922t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm940t",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "ep9312",
+      NULL,
+      {
+        ISA_ARMv4t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv4t
+  },
+  {
+    {
+      "arm10tdmi",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5t
+  },
+  {
+    {
+      "arm1020t",
+      NULL,
+      {
+        ISA_ARMv5t,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5t
+  },
+  {
+    {
+      "arm9e",
+      cpu_opttab_arm9e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm946e-s",
+      cpu_opttab_arm946es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm966e-s",
+      cpu_opttab_arm966es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm968e-s",
+      cpu_opttab_arm968es,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm10e",
+      cpu_opttab_arm10e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm1020e",
+      cpu_opttab_arm1020e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm1022e",
+      cpu_opttab_arm1022e,
+      {
+        ISA_ARMv5te,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "xscale",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_bit_xscale,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "iwmmxt",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_iwmmxt
+  },
+  {
+    {
+      "iwmmxt2",
+      NULL,
+      {
+        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_iwmmxt2
+  },
+  {
+    {
+      "fa606te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fa626te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fmp626",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "fa726te",
+      NULL,
+      {
+        ISA_ARMv5te,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5te
+  },
+  {
+    {
+      "arm926ej-s",
+      cpu_opttab_arm926ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5tej
+  },
+  {
+    {
+      "arm1026ej-s",
+      cpu_opttab_arm1026ejs,
+      {
+        ISA_ARMv5tej,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv5tej
+  },
+  {
+    {
+      "arm1136j-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6j
+  },
+  {
+    {
+      "arm1136jf-s",
+      NULL,
+      {
+        ISA_ARMv6j,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6j
+  },
+  {
+    {
+      "arm1176jz-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6kz
+  },
+  {
+    {
+      "arm1176jzf-s",
+      NULL,
+      {
+        ISA_ARMv6kz,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6kz
+  },
+  {
+    {
+      "mpcorenovfp",
+      NULL,
+      {
+        ISA_ARMv6k,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6k
+  },
+  {
+    {
+      "mpcore",
+      NULL,
+      {
+        ISA_ARMv6k,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6k
+  },
+  {
+    {
+      "arm1156t2-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6t2
+  },
+  {
+    {
+      "arm1156t2f-s",
+      NULL,
+      {
+        ISA_ARMv6t2,
+        ISA_VFPv2,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6t2
+  },
+  {
+    {
+      "cortex-m1",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0plus",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m1.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "cortex-m0plus.small-multiply",
+      NULL,
+      {
+        ISA_ARMv6m,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv6_m
+  },
+  {
+    {
+      "generic-armv7-a",
+      cpu_opttab_genericv7a,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a5",
+      cpu_opttab_cortexa5,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a7",
+      cpu_opttab_cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a8",
+      cpu_opttab_cortexa8,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a9",
+      cpu_opttab_cortexa9,
+      {
+        ISA_ARMv7a,
+        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a12",
+      cpu_opttab_cortexa12,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a15",
+      cpu_opttab_cortexa15,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a17",
+      cpu_opttab_cortexa17,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-r4",
+      NULL,
+      {
+        ISA_ARMv7r,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r4f",
+      NULL,
+      {
+        ISA_ARMv7r,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r5",
+      cpu_opttab_cortexr5,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r7",
+      cpu_opttab_cortexr7,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-r8",
+      cpu_opttab_cortexr8,
+      {
+        ISA_ARMv7r,
+        isa_bit_adiv,
+        ISA_VFPv3,ISA_FP_DBL,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_r
+  },
+  {
+    {
+      "cortex-m7",
+      cpu_opttab_cortexm7,
+      {
+        ISA_ARMv7em,
+        ISA_FPv5,ISA_FP_DBL,
+        isa_quirk_no_volatile_ce,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7e_m
+  },
+  {
+    {
+      "cortex-m4",
+      cpu_opttab_cortexm4,
+      {
+        ISA_ARMv7em,
+        ISA_VFPv4,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7e_m
+  },
+  {
+    {
+      "cortex-m3",
+      NULL,
+      {
+        ISA_ARMv7m,
+        isa_quirk_cm3_ldrd,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_m
+  },
+  {
+    {
+      "marvell-pj4",
+      NULL,
+      {
+        ISA_ARMv7a,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7_a
+  },
+  {
+    {
+      "cortex-a15.cortex-a7",
+      cpu_opttab_cortexa15cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a17.cortex-a7",
+      cpu_opttab_cortexa17cortexa7,
+      {
+        ISA_ARMv7ve,
+        ISA_VFPv4,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv7ve
+  },
+  {
+    {
+      "cortex-a32",
+      cpu_opttab_cortexa32,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a35",
+      cpu_opttab_cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a53",
+      cpu_opttab_cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a57",
+      cpu_opttab_cortexa57,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a72",
+      cpu_opttab_cortexa72,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73",
+      cpu_opttab_cortexa73,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "exynos-m1",
+      cpu_opttab_exynosm1,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "falkor",
+      cpu_opttab_falkor,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "qdf24xx",
+      cpu_opttab_qdf24xx,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "xgene1",
+      cpu_opttab_xgene1,
+      {
+        ISA_ARMv8a,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a57.cortex-a53",
+      cpu_opttab_cortexa57cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a72.cortex-a53",
+      cpu_opttab_cortexa72cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a35",
+      cpu_opttab_cortexa73cortexa35,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-a73.cortex-a53",
+      cpu_opttab_cortexa73cortexa53,
+      {
+        ISA_ARMv8a,
+        isa_bit_crc32,
+        ISA_FP_ARMv8,ISA_NEON,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_a
+  },
+  {
+    {
+      "cortex-m23",
+      NULL,
+      {
+        ISA_ARMv8m_base,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_base
+  },
+  {
+    {
+      "cortex-m33",
+      cpu_opttab_cortexm33,
+      {
+        ISA_ARMv8m_main,
+        isa_bit_ARMv7em,
+        ISA_FPv5,
+        isa_nobit
+      }
+    },
+    TARGET_ARCH_armv8_m_main
+  },
+  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
+};
+static const struct cpu_arch_extension arch_opttab_armv5e[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv5te[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6j[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6k[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6z[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
+  {
+    "fp", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv2", false,
+    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
+  {
+    "vfpv3-d16", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv3", false,
+    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "vfpv3-d16-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv3-fp16", false,
+    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "vfpv4-d16", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "vfpv4", false,
+    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
+  },
+  {
+    "neon", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv3", false,
+    { ISA_VFPv3,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-fp16", false,
+    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "neon-vfpv4", false,
+    { ISA_VFPv4,ISA_NEON, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nosimd", true,
+    { ISA_ALL_SIMD, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
+  {
+    "fp.sp", false,
+    { ISA_VFPv3, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "idiv", false,
+    { isa_bit_adiv, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "noidiv", true,
+    { isa_bit_adiv, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
+  {
+    "fp", false,
+    { ISA_VFPv4, isa_nobit }
+  },
+  {
+    "fpv5", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
+  {
+    "crc", false,
+    { isa_bit_crc32, isa_nobit }
+  },
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
+  {
+    "simd", false,
+    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "fp16", false,
+    { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit }
+  },
+  {
+    "crypto", false,
+    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  {
+    "nocrypto", true,
+    { ISA_ALL_CRYPTO, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
+  {
+    "dsp", false,
+    { isa_bit_ARMv7em, isa_nobit }
+  },
+  {
+    "fp", false,
+    { ISA_FPv5, isa_nobit }
+  },
+  {
+    "fp.dp", false,
+    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
+  },
+  {
+    "nofp", true,
+    { ISA_ALL_FP, isa_nobit }
+  },
+  { NULL, false, {isa_nobit}}
+};
+
+const arch_option all_architectures[] =
+{
+  {
+    "armv2",
+    NULL,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
+  },
+  {
+    "armv2a",
+    NULL,
+    {
+      ISA_ARMv2,isa_bit_mode26,
+      isa_nobit
+    },
+    "2", BASE_ARCH_2,
+    TARGET_CPU_arm2,
+  },
+  {
+    "armv3",
+    NULL,
+    {
+      ISA_ARMv3,isa_bit_mode26,
+      isa_nobit
+    },
+    "3", BASE_ARCH_3,
+    TARGET_CPU_arm6,
+  },
+  {
+    "armv3m",
+    NULL,
+    {
+      ISA_ARMv3m,isa_bit_mode26,
+      isa_nobit
+    },
+    "3M", BASE_ARCH_3M,
+    TARGET_CPU_arm7m,
+  },
+  {
+    "armv4",
+    NULL,
+    {
+      ISA_ARMv4,isa_bit_mode26,
+      isa_nobit
+    },
+    "4", BASE_ARCH_4,
+    TARGET_CPU_arm7tdmi,
+  },
+  {
+    "armv4t",
+    NULL,
+    {
+      ISA_ARMv4t,
+      isa_nobit
+    },
+    "4T", BASE_ARCH_4T,
+    TARGET_CPU_arm7tdmi,
+  },
+  {
+    "armv5",
+    NULL,
+    {
+      ISA_ARMv5,
+      isa_nobit
+    },
+    "5", BASE_ARCH_5,
+    TARGET_CPU_arm10tdmi,
+  },
+  {
+    "armv5t",
+    NULL,
+    {
+      ISA_ARMv5t,
+      isa_nobit
+    },
+    "5T", BASE_ARCH_5T,
+    TARGET_CPU_arm10tdmi,
+  },
+  {
+    "armv5e",
+    arch_opttab_armv5e,
+    {
+      ISA_ARMv5e,
+      isa_nobit
+    },
+    "5E", BASE_ARCH_5E,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv5te",
+    arch_opttab_armv5te,
+    {
+      ISA_ARMv5te,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv5tej",
+    arch_opttab_armv5tej,
+    {
+      ISA_ARMv5tej,
+      isa_nobit
+    },
+    "5TEJ", BASE_ARCH_5TEJ,
+    TARGET_CPU_arm1026ejs,
+  },
+  {
+    "armv6",
+    arch_opttab_armv6,
+    {
+      ISA_ARMv6,
+      isa_nobit
+    },
+    "6", BASE_ARCH_6,
+    TARGET_CPU_arm1136js,
+  },
+  {
+    "armv6j",
+    arch_opttab_armv6j,
+    {
+      ISA_ARMv6j,
+      isa_nobit
+    },
+    "6J", BASE_ARCH_6J,
+    TARGET_CPU_arm1136js,
+  },
+  {
+    "armv6k",
+    arch_opttab_armv6k,
+    {
+      ISA_ARMv6k,
+      isa_nobit
+    },
+    "6K", BASE_ARCH_6K,
+    TARGET_CPU_mpcore,
+  },
+  {
+    "armv6z",
+    arch_opttab_armv6z,
+    {
+      ISA_ARMv6z,
+      isa_nobit
+    },
+    "6Z", BASE_ARCH_6Z,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6kz",
+    arch_opttab_armv6kz,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6zk",
+    arch_opttab_armv6zk,
+    {
+      ISA_ARMv6kz,
+      isa_nobit
+    },
+    "6KZ", BASE_ARCH_6KZ,
+    TARGET_CPU_arm1176jzs,
+  },
+  {
+    "armv6t2",
+    arch_opttab_armv6t2,
+    {
+      ISA_ARMv6t2,
+      isa_nobit
+    },
+    "6T2", BASE_ARCH_6T2,
+    TARGET_CPU_arm1156t2s,
+  },
+  {
+    "armv6-m",
+    NULL,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
+  },
+  {
+    "armv6s-m",
+    NULL,
+    {
+      ISA_ARMv6m,
+      isa_nobit
+    },
+    "6M", BASE_ARCH_6M,
+    TARGET_CPU_cortexm1,
+  },
+  {
+    "armv7",
+    arch_opttab_armv7,
+    {
+      ISA_ARMv7,
+      isa_nobit
+    },
+    "7", BASE_ARCH_7,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7-a",
+    arch_opttab_armv7_a,
+    {
+      ISA_ARMv7a,
+      isa_nobit
+    },
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7ve",
+    arch_opttab_armv7ve,
+    {
+      ISA_ARMv7ve,
+      isa_nobit
+    },
+    "7A", BASE_ARCH_7A,
+    TARGET_CPU_cortexa8,
+  },
+  {
+    "armv7-r",
+    arch_opttab_armv7_r,
+    {
+      ISA_ARMv7r,
+      isa_nobit
+    },
+    "7R", BASE_ARCH_7R,
+    TARGET_CPU_cortexr4,
+  },
+  {
+    "armv7-m",
+    NULL,
+    {
+      ISA_ARMv7m,
+      isa_nobit
+    },
+    "7M", BASE_ARCH_7M,
+    TARGET_CPU_cortexm3,
+  },
+  {
+    "armv7e-m",
+    arch_opttab_armv7e_m,
+    {
+      ISA_ARMv7em,
+      isa_nobit
+    },
+    "7EM", BASE_ARCH_7EM,
+    TARGET_CPU_cortexm4,
+  },
+  {
+    "armv8-a",
+    arch_opttab_armv8_a,
+    {
+      ISA_ARMv8a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8.1-a",
+    arch_opttab_armv8_1_a,
+    {
+      ISA_ARMv8_1a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8.2-a",
+    arch_opttab_armv8_2_a,
+    {
+      ISA_ARMv8_2a,
+      isa_nobit
+    },
+    "8A", BASE_ARCH_8A,
+    TARGET_CPU_cortexa53,
+  },
+  {
+    "armv8-m.base",
+    NULL,
+    {
+      ISA_ARMv8m_base,
+      isa_nobit
+    },
+    "8M_BASE", BASE_ARCH_8M_BASE,
+    TARGET_CPU_cortexm23,
+  },
+  {
+    "armv8-m.main",
+    arch_opttab_armv8_m_main,
+    {
+      ISA_ARMv8m_main,
+      isa_nobit
+    },
+    "8M_MAIN", BASE_ARCH_8M_MAIN,
+    TARGET_CPU_cortexm7,
+  },
+  {
+    "iwmmxt",
+    NULL,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt,
+  },
+  {
+    "iwmmxt2",
+    NULL,
+    {
+      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
+      isa_nobit
+    },
+    "5TE", BASE_ARCH_5TE,
+    TARGET_CPU_iwmmxt2,
+  },
+  {{NULL, NULL, {isa_nobit}},
+   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}
+};
+
+const arm_fpu_desc all_fpus[] =
+{
+  {
+    "vfp",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv2",
+    {
+      ISA_VFPv2,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-fp16",
+    {
+      ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3-d16-fp16",
+    {
+      ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd",
+    {
+      ISA_VFPv3,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv3xd-fp16",
+    {
+      ISA_VFPv3,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "neon",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv3",
+    {
+      ISA_VFPv3,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp16",
+    {
+      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4",
+    {
+      ISA_VFPv4,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-vfpv4",
+    {
+      ISA_VFPv4,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "vfpv4-d16",
+    {
+      ISA_VFPv4,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fpv4-sp-d16",
+    {
+      ISA_VFPv4,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-sp-d16",
+    {
+      ISA_FPv5,
+      isa_nobit
+    }
+  },
+  {
+    "fpv5-d16",
+    {
+      ISA_FPv5,ISA_FP_DBL,
+      isa_nobit
+    }
+  },
+  {
+    "fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+  {
+    "neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_NEON,
+      isa_nobit
+    }
+  },
+  {
+    "crypto-neon-fp-armv8",
+    {
+      ISA_FP_ARMv8,ISA_CRYPTO,
+      isa_nobit
+    }
+  },
+  {
+    "vfp3",
+    {
+      ISA_VFPv3,ISA_FP_D32,
+      isa_nobit
+    }
+  },
+};
 static const struct arm_arch_core_flag arm_arch_core_flags[] =
 {
   {
diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h
index 0e45b23..c2a18e3 100644
--- a/gcc/config/arm/arm-cpu-data.h
+++ b/gcc/config/arm/arm-cpu-data.h
@@ -20,1676 +20,6 @@ 
    License along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-static const cpu_arch_extension cpu_opttab_arm9e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm946es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm966es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm968es[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm10e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1020e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1022e[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_genericv7a[] = {
-  {
-    "simd", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa5[] = {
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa7[] = {
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa8[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa9[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa12[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa15[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa17[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr5[] = {
-  {
-    "nofp.dp", true,
-    { ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexr8[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm7[] = {
-  {
-    "nofp.dp", true,
-    { ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm4[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa32[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa35[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa57[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa72[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_exynosm1[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_falkor[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_qdf24xx[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_xgene1[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_arch_extension cpu_opttab_cortexm33[] = {
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const cpu_option all_cores[] =
-{
-  {
-    {
-      "arm2",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm250",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm3",
-      NULL,
-      {
-        ISA_ARMv2,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv2
-  },
-  {
-    {
-      "arm6",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm60",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm600",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm610",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm620",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7d",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7di",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm70",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm700",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm700i",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm710",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm720",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm710c",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7100",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7500",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7500fe",
-      NULL,
-      {
-        ISA_ARMv3,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3
-  },
-  {
-    {
-      "arm7m",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm7dm",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm7dmi",
-      NULL,
-      {
-        ISA_ARMv3m,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv3m
-  },
-  {
-    {
-      "arm8",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "arm810",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm110",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm1100",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "strongarm1110",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "fa526",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "fa626",
-      NULL,
-      {
-        ISA_ARMv4,isa_bit_mode26,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4
-  },
-  {
-    {
-      "arm7tdmi",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm7tdmi-s",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm710t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm720t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm740t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm9",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm9tdmi",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm920",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm920t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm922t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm940t",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "ep9312",
-      NULL,
-      {
-        ISA_ARMv4t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv4t
-  },
-  {
-    {
-      "arm10tdmi",
-      NULL,
-      {
-        ISA_ARMv5t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5t
-  },
-  {
-    {
-      "arm1020t",
-      NULL,
-      {
-        ISA_ARMv5t,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5t
-  },
-  {
-    {
-      "arm9e",
-      cpu_opttab_arm9e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm946e-s",
-      cpu_opttab_arm946es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm966e-s",
-      cpu_opttab_arm966es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm968e-s",
-      cpu_opttab_arm968es,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm10e",
-      cpu_opttab_arm10e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm1020e",
-      cpu_opttab_arm1020e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm1022e",
-      cpu_opttab_arm1022e,
-      {
-        ISA_ARMv5te,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "xscale",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_bit_xscale,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "iwmmxt",
-      NULL,
-      {
-        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_iwmmxt
-  },
-  {
-    {
-      "iwmmxt2",
-      NULL,
-      {
-        ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_iwmmxt2
-  },
-  {
-    {
-      "fa606te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fa626te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fmp626",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "fa726te",
-      NULL,
-      {
-        ISA_ARMv5te,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5te
-  },
-  {
-    {
-      "arm926ej-s",
-      cpu_opttab_arm926ejs,
-      {
-        ISA_ARMv5tej,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5tej
-  },
-  {
-    {
-      "arm1026ej-s",
-      cpu_opttab_arm1026ejs,
-      {
-        ISA_ARMv5tej,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv5tej
-  },
-  {
-    {
-      "arm1136j-s",
-      NULL,
-      {
-        ISA_ARMv6j,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6j
-  },
-  {
-    {
-      "arm1136jf-s",
-      NULL,
-      {
-        ISA_ARMv6j,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6j
-  },
-  {
-    {
-      "arm1176jz-s",
-      NULL,
-      {
-        ISA_ARMv6kz,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6kz
-  },
-  {
-    {
-      "arm1176jzf-s",
-      NULL,
-      {
-        ISA_ARMv6kz,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6kz
-  },
-  {
-    {
-      "mpcorenovfp",
-      NULL,
-      {
-        ISA_ARMv6k,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6k
-  },
-  {
-    {
-      "mpcore",
-      NULL,
-      {
-        ISA_ARMv6k,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6k
-  },
-  {
-    {
-      "arm1156t2-s",
-      NULL,
-      {
-        ISA_ARMv6t2,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6t2
-  },
-  {
-    {
-      "arm1156t2f-s",
-      NULL,
-      {
-        ISA_ARMv6t2,
-        ISA_VFPv2,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6t2
-  },
-  {
-    {
-      "cortex-m1",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0plus",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m1.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "cortex-m0plus.small-multiply",
-      NULL,
-      {
-        ISA_ARMv6m,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv6_m
-  },
-  {
-    {
-      "generic-armv7-a",
-      cpu_opttab_genericv7a,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a5",
-      cpu_opttab_cortexa5,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a7",
-      cpu_opttab_cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a8",
-      cpu_opttab_cortexa8,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a9",
-      cpu_opttab_cortexa9,
-      {
-        ISA_ARMv7a,
-        ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a12",
-      cpu_opttab_cortexa12,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a15",
-      cpu_opttab_cortexa15,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a17",
-      cpu_opttab_cortexa17,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-r4",
-      NULL,
-      {
-        ISA_ARMv7r,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r4f",
-      NULL,
-      {
-        ISA_ARMv7r,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r5",
-      cpu_opttab_cortexr5,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r7",
-      cpu_opttab_cortexr7,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-r8",
-      cpu_opttab_cortexr8,
-      {
-        ISA_ARMv7r,
-        isa_bit_adiv,
-        ISA_VFPv3,ISA_FP_DBL,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_r
-  },
-  {
-    {
-      "cortex-m7",
-      cpu_opttab_cortexm7,
-      {
-        ISA_ARMv7em,
-        ISA_FPv5,ISA_FP_DBL,
-        isa_quirk_no_volatile_ce,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7e_m
-  },
-  {
-    {
-      "cortex-m4",
-      cpu_opttab_cortexm4,
-      {
-        ISA_ARMv7em,
-        ISA_VFPv4,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7e_m
-  },
-  {
-    {
-      "cortex-m3",
-      NULL,
-      {
-        ISA_ARMv7m,
-        isa_quirk_cm3_ldrd,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_m
-  },
-  {
-    {
-      "marvell-pj4",
-      NULL,
-      {
-        ISA_ARMv7a,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7_a
-  },
-  {
-    {
-      "cortex-a15.cortex-a7",
-      cpu_opttab_cortexa15cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a17.cortex-a7",
-      cpu_opttab_cortexa17cortexa7,
-      {
-        ISA_ARMv7ve,
-        ISA_VFPv4,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv7ve
-  },
-  {
-    {
-      "cortex-a32",
-      cpu_opttab_cortexa32,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a35",
-      cpu_opttab_cortexa35,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a53",
-      cpu_opttab_cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a57",
-      cpu_opttab_cortexa57,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a72",
-      cpu_opttab_cortexa72,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73",
-      cpu_opttab_cortexa73,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "exynos-m1",
-      cpu_opttab_exynosm1,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "falkor",
-      cpu_opttab_falkor,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "qdf24xx",
-      cpu_opttab_qdf24xx,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "xgene1",
-      cpu_opttab_xgene1,
-      {
-        ISA_ARMv8a,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a57.cortex-a53",
-      cpu_opttab_cortexa57cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a72.cortex-a53",
-      cpu_opttab_cortexa72cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73.cortex-a35",
-      cpu_opttab_cortexa73cortexa35,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-a73.cortex-a53",
-      cpu_opttab_cortexa73cortexa53,
-      {
-        ISA_ARMv8a,
-        isa_bit_crc32,
-        ISA_FP_ARMv8,ISA_NEON,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_a
-  },
-  {
-    {
-      "cortex-m23",
-      NULL,
-      {
-        ISA_ARMv8m_base,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_m_base
-  },
-  {
-    {
-      "cortex-m33",
-      cpu_opttab_cortexm33,
-      {
-        ISA_ARMv8m_main,
-        isa_bit_ARMv7em,
-        ISA_FPv5,
-        isa_nobit
-      }
-    },
-    TARGET_ARCH_armv8_m_main
-  },
-  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
-};
 static const cpu_tune all_tunes[] =
 {
   { /* arm2.  */
@@ -2244,913 +574,3 @@  static const cpu_tune all_tunes[] =
   },
   {TARGET_CPU_arm_none, 0, NULL}
 };
-static const struct cpu_arch_extension arch_opttab_armv5e[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv5te[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6j[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6k[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6z[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
-  {
-    "fp", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv2", false,
-    { ISA_VFPv2,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7[] = {
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
-  {
-    "vfpv3-d16", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv3", false,
-    { ISA_VFPv3,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "vfpv3-d16-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv3-fp16", false,
-    { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "vfpv4-d16", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_VFPv4,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "vfpv4", false,
-    { ISA_VFPv4,ISA_FP_D32, isa_nobit }
-  },
-  {
-    "neon", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv3", false,
-    { ISA_VFPv3,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-fp16", false,
-    { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "neon-vfpv4", false,
-    { ISA_VFPv4,ISA_NEON, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nosimd", true,
-    { ISA_ALL_SIMD, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
-  {
-    "fp.sp", false,
-    { ISA_VFPv3, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_VFPv3,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "idiv", false,
-    { isa_bit_adiv, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "noidiv", true,
-    { isa_bit_adiv, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
-  {
-    "fp", false,
-    { ISA_VFPv4, isa_nobit }
-  },
-  {
-    "fpv5", false,
-    { ISA_FPv5, isa_nobit }
-  },
-  {
-    "fp.dp", false,
-    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
-  {
-    "crc", false,
-    { isa_bit_crc32, isa_nobit }
-  },
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
-  {
-    "simd", false,
-    { ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "fp16", false,
-    { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit }
-  },
-  {
-    "crypto", false,
-    { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  {
-    "nocrypto", true,
-    { ISA_ALL_CRYPTO, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
-  {
-    "dsp", false,
-    { isa_bit_ARMv7em, isa_nobit }
-  },
-  {
-    "fp", false,
-    { ISA_FPv5, isa_nobit }
-  },
-  {
-    "fp.dp", false,
-    { ISA_FPv5,ISA_FP_DBL, isa_nobit }
-  },
-  {
-    "nofp", true,
-    { ISA_ALL_FP, isa_nobit }
-  },
-  { NULL, false, {isa_nobit}}
-};
-
-static const struct arch_option all_architectures[] =
-{
-  {
-    "armv2",
-    NULL,
-    {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
-    },
-    "2", BASE_ARCH_2,
-    TARGET_CPU_arm2,
-  },
-  {
-    "armv2a",
-    NULL,
-    {
-      ISA_ARMv2,isa_bit_mode26,
-      isa_nobit
-    },
-    "2", BASE_ARCH_2,
-    TARGET_CPU_arm2,
-  },
-  {
-    "armv3",
-    NULL,
-    {
-      ISA_ARMv3,isa_bit_mode26,
-      isa_nobit
-    },
-    "3", BASE_ARCH_3,
-    TARGET_CPU_arm6,
-  },
-  {
-    "armv3m",
-    NULL,
-    {
-      ISA_ARMv3m,isa_bit_mode26,
-      isa_nobit
-    },
-    "3M", BASE_ARCH_3M,
-    TARGET_CPU_arm7m,
-  },
-  {
-    "armv4",
-    NULL,
-    {
-      ISA_ARMv4,isa_bit_mode26,
-      isa_nobit
-    },
-    "4", BASE_ARCH_4,
-    TARGET_CPU_arm7tdmi,
-  },
-  {
-    "armv4t",
-    NULL,
-    {
-      ISA_ARMv4t,
-      isa_nobit
-    },
-    "4T", BASE_ARCH_4T,
-    TARGET_CPU_arm7tdmi,
-  },
-  {
-    "armv5",
-    NULL,
-    {
-      ISA_ARMv5,
-      isa_nobit
-    },
-    "5", BASE_ARCH_5,
-    TARGET_CPU_arm10tdmi,
-  },
-  {
-    "armv5t",
-    NULL,
-    {
-      ISA_ARMv5t,
-      isa_nobit
-    },
-    "5T", BASE_ARCH_5T,
-    TARGET_CPU_arm10tdmi,
-  },
-  {
-    "armv5e",
-    arch_opttab_armv5e,
-    {
-      ISA_ARMv5e,
-      isa_nobit
-    },
-    "5E", BASE_ARCH_5E,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv5te",
-    arch_opttab_armv5te,
-    {
-      ISA_ARMv5te,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv5tej",
-    arch_opttab_armv5tej,
-    {
-      ISA_ARMv5tej,
-      isa_nobit
-    },
-    "5TEJ", BASE_ARCH_5TEJ,
-    TARGET_CPU_arm1026ejs,
-  },
-  {
-    "armv6",
-    arch_opttab_armv6,
-    {
-      ISA_ARMv6,
-      isa_nobit
-    },
-    "6", BASE_ARCH_6,
-    TARGET_CPU_arm1136js,
-  },
-  {
-    "armv6j",
-    arch_opttab_armv6j,
-    {
-      ISA_ARMv6j,
-      isa_nobit
-    },
-    "6J", BASE_ARCH_6J,
-    TARGET_CPU_arm1136js,
-  },
-  {
-    "armv6k",
-    arch_opttab_armv6k,
-    {
-      ISA_ARMv6k,
-      isa_nobit
-    },
-    "6K", BASE_ARCH_6K,
-    TARGET_CPU_mpcore,
-  },
-  {
-    "armv6z",
-    arch_opttab_armv6z,
-    {
-      ISA_ARMv6z,
-      isa_nobit
-    },
-    "6Z", BASE_ARCH_6Z,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6kz",
-    arch_opttab_armv6kz,
-    {
-      ISA_ARMv6kz,
-      isa_nobit
-    },
-    "6KZ", BASE_ARCH_6KZ,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6zk",
-    arch_opttab_armv6zk,
-    {
-      ISA_ARMv6kz,
-      isa_nobit
-    },
-    "6KZ", BASE_ARCH_6KZ,
-    TARGET_CPU_arm1176jzs,
-  },
-  {
-    "armv6t2",
-    arch_opttab_armv6t2,
-    {
-      ISA_ARMv6t2,
-      isa_nobit
-    },
-    "6T2", BASE_ARCH_6T2,
-    TARGET_CPU_arm1156t2s,
-  },
-  {
-    "armv6-m",
-    NULL,
-    {
-      ISA_ARMv6m,
-      isa_nobit
-    },
-    "6M", BASE_ARCH_6M,
-    TARGET_CPU_cortexm1,
-  },
-  {
-    "armv6s-m",
-    NULL,
-    {
-      ISA_ARMv6m,
-      isa_nobit
-    },
-    "6M", BASE_ARCH_6M,
-    TARGET_CPU_cortexm1,
-  },
-  {
-    "armv7",
-    arch_opttab_armv7,
-    {
-      ISA_ARMv7,
-      isa_nobit
-    },
-    "7", BASE_ARCH_7,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7-a",
-    arch_opttab_armv7_a,
-    {
-      ISA_ARMv7a,
-      isa_nobit
-    },
-    "7A", BASE_ARCH_7A,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7ve",
-    arch_opttab_armv7ve,
-    {
-      ISA_ARMv7ve,
-      isa_nobit
-    },
-    "7A", BASE_ARCH_7A,
-    TARGET_CPU_cortexa8,
-  },
-  {
-    "armv7-r",
-    arch_opttab_armv7_r,
-    {
-      ISA_ARMv7r,
-      isa_nobit
-    },
-    "7R", BASE_ARCH_7R,
-    TARGET_CPU_cortexr4,
-  },
-  {
-    "armv7-m",
-    NULL,
-    {
-      ISA_ARMv7m,
-      isa_nobit
-    },
-    "7M", BASE_ARCH_7M,
-    TARGET_CPU_cortexm3,
-  },
-  {
-    "armv7e-m",
-    arch_opttab_armv7e_m,
-    {
-      ISA_ARMv7em,
-      isa_nobit
-    },
-    "7EM", BASE_ARCH_7EM,
-    TARGET_CPU_cortexm4,
-  },
-  {
-    "armv8-a",
-    arch_opttab_armv8_a,
-    {
-      ISA_ARMv8a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8.1-a",
-    arch_opttab_armv8_1_a,
-    {
-      ISA_ARMv8_1a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8.2-a",
-    arch_opttab_armv8_2_a,
-    {
-      ISA_ARMv8_2a,
-      isa_nobit
-    },
-    "8A", BASE_ARCH_8A,
-    TARGET_CPU_cortexa53,
-  },
-  {
-    "armv8-m.base",
-    NULL,
-    {
-      ISA_ARMv8m_base,
-      isa_nobit
-    },
-    "8M_BASE", BASE_ARCH_8M_BASE,
-    TARGET_CPU_cortexm23,
-  },
-  {
-    "armv8-m.main",
-    arch_opttab_armv8_m_main,
-    {
-      ISA_ARMv8m_main,
-      isa_nobit
-    },
-    "8M_MAIN", BASE_ARCH_8M_MAIN,
-    TARGET_CPU_cortexm7,
-  },
-  {
-    "iwmmxt",
-    NULL,
-    {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_iwmmxt,
-  },
-  {
-    "iwmmxt2",
-    NULL,
-    {
-      ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2,
-      isa_nobit
-    },
-    "5TE", BASE_ARCH_5TE,
-    TARGET_CPU_iwmmxt2,
-  },
-  {{NULL, NULL, {isa_nobit}},
-   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}
-};
-
-const struct arm_fpu_desc all_fpus[] =
-{
-  {
-    "vfp",
-    {
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv2",
-    {
-      ISA_VFPv2,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3",
-    {
-      ISA_VFPv3,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-fp16",
-    {
-      ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-d16",
-    {
-      ISA_VFPv3,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3-d16-fp16",
-    {
-      ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3xd",
-    {
-      ISA_VFPv3,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv3xd-fp16",
-    {
-      ISA_VFPv3,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "neon",
-    {
-      ISA_VFPv3,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "neon-vfpv3",
-    {
-      ISA_VFPv3,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "neon-fp16",
-    {
-      ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv4",
-    {
-      ISA_VFPv4,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "neon-vfpv4",
-    {
-      ISA_VFPv4,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "vfpv4-d16",
-    {
-      ISA_VFPv4,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "fpv4-sp-d16",
-    {
-      ISA_VFPv4,
-      isa_nobit
-    }
-  },
-  {
-    "fpv5-sp-d16",
-    {
-      ISA_FPv5,
-      isa_nobit
-    }
-  },
-  {
-    "fpv5-d16",
-    {
-      ISA_FPv5,ISA_FP_DBL,
-      isa_nobit
-    }
-  },
-  {
-    "fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-  {
-    "neon-fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_NEON,
-      isa_nobit
-    }
-  },
-  {
-    "crypto-neon-fp-armv8",
-    {
-      ISA_FP_ARMv8,ISA_CRYPTO,
-      isa_nobit
-    }
-  },
-  {
-    "vfp3",
-    {
-      ISA_VFPv3,ISA_FP_D32,
-      isa_nobit
-    }
-  },
-};
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index ada2503..f30b81e 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -513,4 +513,16 @@  struct cpu_option
   enum arch_type arch;
 };
 
+extern const arch_option all_architectures[];
+extern const cpu_option all_cores[];
+
+const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *,
+					     const char *);
+const arch_option *arm_parse_arch_option_name (const arch_option *,
+					       const char *, const char *);
+void arm_parse_option_features (sbitmap, const cpu_arch_option *,
+				const char *);
+
+void arm_initialize_isa (sbitmap, const enum isa_feature *);
+
 #endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 5664145..1716b38 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3046,194 +3046,6 @@  arm_option_override_internal (struct gcc_options *opts,
 #endif
 }
 
-/* Convert a static initializer array of feature bits to sbitmap
-   representation.  */
-static void
-arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
-{
-  bitmap_clear (isa);
-  while (*isa_bits != isa_nobit)
-    bitmap_set_bit (isa, *(isa_bits++));
-}
-
-/* List the premitted CPU option names.  If TARGET is a near miss for an
-   entry, print out the suggested alternative.  */
-static void
-arm_print_hint_for_cpu_option (const char *target,
-			       const cpu_option *list)
-{
-  auto_vec<const char*> candidates;
-  for (; list->common.name != NULL; list++)
-    candidates.safe_push (list->common.name);
-  char *s;
-  const char *hint = candidates_list_and_hint (target, s, candidates);
-  if (hint)
-    inform (input_location, "valid arguments are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid arguments are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse the base component of a CPU selection in LIST.  Return a
-   pointer to the entry in the architecture table.  OPTNAME is the
-   name of the option we are parsing and can be used if a diagnostic
-   is needed.  */
-static const cpu_option *
-arm_parse_cpu_option_name (const cpu_option *list, const char *optname,
-		       const char *target)
-{
-  const cpu_option *entry;
-  const char *end  = strchr (target, '+');
-  size_t len = end ? end - target : strlen (target);
-
-  for (entry = list; entry->common.name != NULL; entry++)
-    {
-      if (strncmp (entry->common.name, target, len) == 0
-	  && entry->common.name[len] == '\0')
-	return entry;
-    }
-
-  error_at (input_location, "unrecognized %s target: %s", optname, target);
-  arm_print_hint_for_cpu_option (target, list);
-  return NULL;
-}
-
-/* List the premitted architecture option names.  If TARGET is a near
-   miss for an entry, print out the suggested alternative.  */
-static void
-arm_print_hint_for_arch_option (const char *target,
-			       const arch_option *list)
-{
-  auto_vec<const char*> candidates;
-  for (; list->common.name != NULL; list++)
-    candidates.safe_push (list->common.name);
-  char *s;
-  const char *hint = candidates_list_and_hint (target, s, candidates);
-  if (hint)
-    inform (input_location, "valid arguments are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid arguments are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse the base component of a CPU or architecture selection in
-   LIST.  Return a pointer to the entry in the architecture table.
-   OPTNAME is the name of the option we are parsing and can be used if
-   a diagnostic is needed.  */
-static const arch_option *
-arm_parse_arch_option_name (const arch_option *list, const char *optname,
-			    const char *target)
-{
-  const arch_option *entry;
-  const char *end  = strchr (target, '+');
-  size_t len = end ? end - target : strlen (target);
-
-  for (entry = list; entry->common.name != NULL; entry++)
-    {
-      if (strncmp (entry->common.name, target, len) == 0
-	  && entry->common.name[len] == '\0')
-	return entry;
-    }
-
-  error_at (input_location, "unrecognized %s target: %s", optname, target);
-  arm_print_hint_for_arch_option (target, list);
-  return NULL;
-}
-
-/* OPT isn't a recognized feature.  Print a suitable error message and
-   suggest a possible value.  Always print the list of premitted
-   values.  */
-static void
-arm_unrecognized_feature (const char *opt, size_t len,
-			  const cpu_arch_option *target)
-{
-  char *this_opt = XALLOCAVEC (char, len+1);
-  auto_vec<const char*> candidates;
-
-  strncpy (this_opt, opt, len);
-  this_opt[len] = 0;
-
-  error_at (input_location, "%qs does not support feature %qs", target->name,
-	    this_opt);
-  for (const cpu_arch_extension *list = target->extensions;
-       list->name != NULL;
-       list++)
-    candidates.safe_push (list->name);
-
-  char *s;
-  const char *hint = candidates_list_and_hint (this_opt, s, candidates);
-
-  if (hint)
-    inform (input_location, "valid feature names are: %s; did you mean %qs?",
-	    s, hint);
-  else
-    inform (input_location, "valid feature names are: %s", s);
-
-  XDELETEVEC (s);
-}
-
-/* Parse any feature extensions to add to (or remove from) the
-   permitted ISA selection.  */
-static void
-arm_parse_option_features (sbitmap isa, const cpu_arch_option *target,
-			   const char *opts_in)
-{
-  const char *opts = opts_in;
-
-  if (!opts)
-    return;
-
-  if (!target->extensions)
-    {
-      error_at (input_location, "%s does not take any feature options",
-		target->name);
-      return;
-    }
-
-  while (opts)
-    {
-      gcc_assert (*opts == '+');
-      const struct cpu_arch_extension *entry;
-      const char *end = strchr (++opts, '+');
-      size_t len = end ? end - opts : strlen (opts);
-      bool matched = false;
-
-      for (entry = target->extensions;
-	   !matched && entry->name != NULL;
-	   entry++)
-	{
-	  if (strncmp (entry->name, opts, len) == 0
-	      && entry->name[len] == '\0')
-	    {
-	      if (isa)
-		{
-		  const enum isa_feature *f = entry->isa_bits;
-		  if (entry->remove)
-		    {
-		      while (*f != isa_nobit)
-			bitmap_clear_bit (isa, *(f++));
-		    }
-		  else
-		    {
-		      while (*f != isa_nobit)
-			bitmap_set_bit (isa, *(f++));
-		    }
-		}
-	      matched = true;
-	    }
-	}
-
-      if (!matched)
-	arm_unrecognized_feature (opts, len, target);
-
-      opts = end;
-    }
-}
-
 static sbitmap isa_all_fpubits;
 static sbitmap isa_quirkbits;
 
@@ -30898,7 +30710,7 @@  arm_identify_fpu_from_isa (sbitmap isa)
   if (bitmap_empty_p (fpubits))
     return "softvfp";
 
-  for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++)
+  for (unsigned int i = 0; i < TARGET_FPU_auto; i++)
     {
       arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits);
       if (bitmap_equal_p (fpubits, cand_fpubits))
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index 57565bd..70b8938 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -128,6 +128,39 @@  function gen_headers () {
 function gen_data () {
     boilerplate("C")
 
+    print "static const cpu_tune all_tunes[] ="
+    print "{"
+
+    ncpus = split (cpu_list, cpus)
+
+    for (n = 1; n <= ncpus; n++) {
+	print "  { /* " cpus[n] ".  */"
+	# scheduler
+	if (cpus[n] in cpu_tune_for) {
+	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
+		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
+		      " for CPU " cpus[n])
+	    }
+	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
+	} else {
+	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
+	}
+	# tune_flags
+	if (cpus[n] in cpu_tune_flags) {
+	    print "    (" cpu_tune_flags[cpus[n]] "),"
+	} else print "    0,"
+	# tune
+	print "    &arm_" cpu_cost[cpus[n]] "_tune"
+	print "  },"
+    }
+    print "  {TARGET_CPU_arm_none, 0, NULL}"
+    print "};"
+    
+}
+
+function gen_comm_data () {
+    boilerplate("C")
+
     ncpus = split (cpu_list, cpus)
 
     for (n = 1; n <= ncpus; n++) {
@@ -147,7 +180,7 @@  function gen_data () {
 	}
     }
 
-    print "static const cpu_option all_cores[] ="
+    print "const cpu_option all_cores[] ="
     print "{"
 
     for (n = 1; n <= ncpus; n++) {
@@ -188,32 +221,6 @@  function gen_data () {
     print "  {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}"
     print "};"
 
-    print "static const cpu_tune all_tunes[] ="
-    print "{"
-
-    for (n = 1; n <= ncpus; n++) {
-	print "  { /* " cpus[n] ".  */"
-	# scheduler
-	if (cpus[n] in cpu_tune_for) {
-	    if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) {
-		fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \
-		      " for CPU " cpus[n])
-	    }
-	    print "    TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] ","
-	} else {
-	    print "    TARGET_CPU_" cpu_cnames[cpus[n]] ","
-	}
-	# tune_flags
-	if (cpus[n] in cpu_tune_flags) {
-	    print "    (" cpu_tune_flags[cpus[n]] "),"
-	} else print "    0,"
-	# tune
-	print "    &arm_" cpu_cost[cpus[n]] "_tune"
-	print "  },"
-    }
-    print "  {TARGET_CPU_arm_none, 0, NULL}"
-    print "};"
-    
     narchs = split (arch_list, archs)
 
     for (n = 1; n <= narchs; n++) {
@@ -233,7 +240,7 @@  function gen_data () {
 	}
     }
 
-    print "static const struct arch_option all_architectures[] ="
+    print "const arch_option all_architectures[] ="
     print "{"
 
     for (n = 1; n <= narchs; n++) {
@@ -265,7 +272,7 @@  function gen_data () {
     print "   NULL, BASE_ARCH_0, TARGET_CPU_arm_none}"
     print "};\n"
 
-    print "const struct arm_fpu_desc all_fpus[] ="
+    print "const arm_fpu_desc all_fpus[] ="
     print "{"
 
     nfpus = split (fpu_list, fpus)
@@ -281,10 +288,6 @@  function gen_data () {
     }
 
     print "};"
-}
-
-function gen_comm_data () {
-    boilerplate("C")
 
     print "static const struct arm_arch_core_flag arm_arch_core_flags[] ="
     print "{"