From patchwork Mon Jun 19 15:45:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105864 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp913216obh; Mon, 19 Jun 2017 08:47:49 -0700 (PDT) X-Received: by 10.84.129.65 with SMTP id 59mr29967145plb.166.1497887269709; Mon, 19 Jun 2017 08:47:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497887269; cv=none; d=google.com; s=arc-20160816; b=pl6uzu4fvF+qe40dXeTEaXXNi1at66Z1WhvtpeMwQd0ZkEP3KeKw47AfzX8CTuTl+Y ABKmMfGhwyiIVGsw7qTroHQGs7FrSXchHebSRPWRIZz0WYGI57a8JxFT+e1N04oOfjm+ WVcJb/S4bScSKYSifJLRvEwP2TioAVmLtmv2Ju9MY7Dd1z+gEZcDVdQDO6H1k8GKFh9Y odVGbfDr4Q5rgj8OvxtMhMJcEB0tLgbGqcEtrSiADSUba+gKU308pomUNkHNfuBiAtID +QNUXInB90VtCA6NxjBHOHRJK7HNfuuAPjOqAfBid2zdtkSFY5kj5uJuCWRTpAlAoglw 9CSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=NUZEZB2PDbWueiswrnBgYIb02meOL45ZdF5lOd8RInM=; b=vALJdpLIpCEKMOOvOOlL33PpWSmtKRNlrqS2VX8cI8mohWPg8F+8h1AX8lgtzXssT+ +f2NUYHPZ83SZegLk3VIYebpjuuZA7suP/dmrOYlaNOqGJhpw7nTVsw+vJ1XHVWuDdq9 OahRjrjHAeBWc2P07Zq87O/5aAiwzZndsBkA3FveTsJ/+tuak8L/t3ALzrXnkRFsrVIz +I+i1JO2AeQoCNB3byLLarifCUg1QjJz3/3aB5irQBFbXgPf7rgvofpw7vW0b0AePe7k SBuVMR6/WLgo9FekpPgLq1zH7USG1x3QUXREcL2vMD8wiomO0S6ak2EFX7mRSPJPboBf hFVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k1si370505pln.567.2017.06.19.08.47.49; Mon, 19 Jun 2017 08:47:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbdFSPro (ORCPT + 8 others); Mon, 19 Jun 2017 11:47:44 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8761 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753070AbdFSPrn (ORCPT ); Mon, 19 Jun 2017 11:47:43 -0400 Received: from 172.30.72.54 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQP39130; Mon, 19 Jun 2017 23:47:29 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Mon, 19 Jun 2017 23:47:19 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Mon, 19 Jun 2017 16:45:00 +0100 Message-ID: <20170619154500.92336-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170619154500.92336-1-shameerali.kolothum.thodi@huawei.com> References: <20170619154500.92336-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.5947F212.0153, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72177e5c273007e981b7bb8714aa68f7 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..f03c63b 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1904,14 +1905,31 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_device *smmu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); + + if (smmu && (smmu->options & ARM_SMMU_OPT_RESV_HW_MSI) && + dev_is_pci(dev)) { + int ret = -EINVAL; + + if (!is_of_node(smmu->dev->fwnode)) + ret = iort_iommu_its_get_resv_regions(dev, head); - list_add_tail(®ion->list, head); + if (ret) { + dev_warn(dev, "HW MSI region resv failed: %d\n", ret); + return; + } + } else { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2611,6 +2629,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;