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[209.132.180.67]) by mx.google.com with ESMTP id p75si12601954pfk.288.2017.06.21.02.23.35; Wed, 21 Jun 2017 02:23:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-usb-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-usb-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-usb-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752804AbdFUJXV (ORCPT + 4 others); Wed, 21 Jun 2017 05:23:21 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8370 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752227AbdFUJXS (ORCPT ); Wed, 21 Jun 2017 05:23:18 -0400 Received: from 172.30.72.53 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APT48848; Wed, 21 Jun 2017 17:23:11 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Wed, 21 Jun 2017 17:23:02 +0800 From: Jiancheng Xue To: , , , , , CC: , , , , , , , Jiancheng Xue Subject: [PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy Date: Wed, 21 Jun 2017 17:00:42 +0800 Message-ID: <1498035645-22804-3-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.594A3B00.007E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 266b03c27809d6288635e9dad0762eea Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add support for hisi-inno-usb2 phy. Signed-off-by: Jiancheng Xue --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 0000000..21f8208 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,36 @@ +HiSilicon INNO USB2 PHY +----------------------- +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy", +- #phy-cells: Must be 0 +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy. +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk. +- resets: List of phandle and reset specifier pairs for each reset signal in +reset-names. +- reset-names: Should be "por_rst" and "test_rst". The test_rst only +exists in some of SOCs, so it is optional. + +Phy node can include up to four subnodes. Each subnode represents one port. +The required properties of port node are as follows: +- clocks: Phandle and clock specifier pair for utmi_clock. +- resets: List of phandle and reset specifier pairs for port reset and utmi reset. +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst" + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: +usb_phy: phy { + compatible = "hisilicon,inno_usb2_phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + clocks = <&crg USB2_REF_CLK>; + resets = <&crg 0xb4 2>; + reset-names = "por_rst"; + port0 { + clocks = <&crg USB2_UTMI0_CLK>; + resets = <&crg 0xb4 5>, <&crg 0xb4 1>; + reset-names = "port_rst", "utmi_rst"; + }; + };